XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 230
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
INTEL
Quantity:
340
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
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Chapter 6: SelectIO Resources
230
DCI Usage Examples
4.
5.
6.
7.
The behavior of a DCI 3-state outputs is as follows:
If a LVDCI or LVDCI_DV2 driver is in 3-state, the driver is 3-stated. If a driver with single
or split termination is in 3-state, the driver is 3-stated but the termination resistor remains.
The following section lists actions that must be taken for each DCI I/O standard.
•
•
•
•
The value of the external reference resistors should be selected to give the desired
output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then
the external reference resistors should be 50 Ω .
The values of the reference resistors must be within the supported range
(20 Ω – 100 Ω).
Follow the DCI I/O banking rules:
a.
b. V
c.
d. No more than one DCI I/O standard using split termination type is allowed per
e.
Master DCI is not supported in Banks 1 and 2.
Figure 6-16
HSTL_III_DCI, and HSTL_IV_DCI I/O standards.
Figure 6-17
SSTL2_II_DCI I/O standards.
DCI outputs that do not require reference resistors on VRP/VRN:
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_III_DCI_18
SSTL2_I_DCI
SSTL18_I_DCI
DCI inputs that do not require reference resistors on VRP/VRN:
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
V
No more than one DCI I/O standard using single termination type is allowed per
bank.
bank.
Single termination and split termination, controlled impedance driver, and
controlled impedance driver with half impedance can co-exist in the same bank.
REF
CCO
must be compatible for all of the inputs in the same bank.
must be compatible for all of the inputs and outputs in the same bank.
provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI,
provides examples illustrating the use of the SSTL2_I_DCI and
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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