XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 368
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
INTEL
Quantity:
340
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
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Quantity:
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Chapter 8: Advanced SelectIO Logic Resources
368
Bitslip Timing Model and Parameters
This section discusses the timing models associated with the Bitslip controller in a 1:4 DDR
configuration. Data (D) is a repeating, 4-bit training pattern ABCD. ABCD could appear at
the parallel outputs Q1–Q4 of the ISERDES in four possible ways: ABCD, BCDA, CDAB,
and DABC. Only one of these four alignments of the parallel word makes sense to the
user's downstream logic that reads the data from the Q1–Q4 outputs of the ISERDES. In
this case, ABCD is assumed to be the word alignment that makes sense. Asserting Bitslip
allows the user to see all possible configurations of ABCD and then choose the expected
alignment (ABCD).
corresponding re-alignments of the ISERDES parallel outputs Q1–Q4.
X-Ref Target - Figure 8-12
Clock Event 1
The entire first word CDAB has been sampled into the input side registers of the ISERDES.
The Bitslip pin is not asserted; the word propagates through the ISERDES without any
realignment.
Clock Event 2
The second word CDAB has been sampled into the input side registers of the ISERDES.
The Bitslip pin is asserted, which causes the Bitslip controller to shift all bits internally by
one bit to the right.
Clock Event 3
The third word CDAB has been sampled into the input side registers of the ISERDES. The
Bitslip pin is asserted for a second time, which causes the Bitslip controller to shift all bits
internally by three bits to the left.
On this same edge of CLKDIV, the first word sampled is presented to Q1–Q4 without any
realignment. The actual bits from the input stream that appear at the Q1–Q4 outputs
during this cycle are shown in A of
BITSLIP
CLKDIV
Q4–Q1
CLK
D
Figure 8-12
C D A B C D
Figure 8-12: Bitslip Timing Diagram
www.xilinx.com
shows the timing of two Bitslip operations and the
1
Figure
Bitslip1
A B C D A B
8-13.
2
Bitslip2
CDAB
C D
3
BCDA
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
4
ug190_8_12_100307
ABCD
5
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