XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 332
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
INTEL
Quantity:
340
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-10
332
Figure 7-10: Basic Sections of Blocks Related to IODELAY Turnaround with Pertinent Paths Shown
CLK
CLK
Q1
Q2
D1
D2
T1
T2
IODELAY Turnaround Time Usage Model
ODDR
ODDR
IDDR
When using IODELAY in bidirectional mode, the turnaround time needs to be considered.
Figure 7-10
that applies to one use of the bidirectional IODELAY functionality.
When DELAY_SRC = IO, MUXE and MUXF dynamically selects ODATAIN or IDATAIN
and ODELAY_VALUE or IDELAY_VALUE inside the IODELAY block.
The following Verilog code segment is used for demonstrating bidirectional IODELAY:
IDDR #(
)IDDR_INST (
);
IOBUF #(
)IOBUF_INST (
);
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC")
.C(clk),
.CE(1'b1),
.D(DATAOUT),
.R(1'b0),
.S(1'b0),
.Q1(Q1),
.Q2(Q2)
.IOSTANDARD ("LVCMOS25")
.I(DATAOUT),
.T(TSCONTROL),
.O(IDATAIN),
.IO(IOPAD_DATA)
shows a simplified block diagram of the IODELAY in the Virtex-5 FPGA IOB
DATAOUT
ODATAIN
IODELAY
Delay
Chain
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_01_081407
PAD
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