XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 340
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
INTEL
Quantity:
340
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-17
340
1 Clock Region
IDELAYCTRL
IDELAYCTRL Usage and Design Guidelines
This section describes using the IDELAYCTRL modules, design guidelines, and
recommended usage in Virtex-5 devices.
Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools auto-
replicate IDELAYCTRL instances throughout the entire device. When IDELAYCTRL
instances are replicated to clock regions but not used, the extra instances are trimmed out
of the design automatically by the ISE software. The signals connected to the RST and
REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the
corresponding input ports of the replicated IDELAYCTRL instances.
There are two special cases:
1.
Figure 7-17: Relative Locations of IDELAYCTRL Modules
When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided in
the Libraries Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
Column
Left I/O
Figure
7-18.
www.xilinx.com
Center I/O
Column
CMT
CMT
Configuration
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Right I/O
Column
ug190_7_12_041206
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