XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 51
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
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Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
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DCM Ports
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DCM_ADV Primitive
DCM Clock Input Ports
Source Clock Input - CLKIN
The DCM_ADV primitive has access to all DCM features and ports available in
DCM_BASE plus additional ports for the dynamic reconfiguration feature. It is a superset
of the DCM_BASE primitive. DCM_ADV uses all the DCM features including clock
deskew, frequency synthesis, fixed or variable phase shifting, and dynamic
reconfiguration.
Table 2-3: DCM_ADV Primitive
There are four types of DCM ports available in the Virtex-5 architecture:
•
•
•
•
The source clock (CLKIN) input pin provides the source clock to the DCM. The CLKIN
frequency must fall in the ranges specified in the Virtex-5 FPGA Data Sheet. If CLKIN is
stopped for 100 ms or longer, the DCM powers down. The clock input signal comes from
one of these buffers:
1.
2.
3.
4.
Clock Input
Control and Data Input
Clock Output
Status and Data Output
DCM Clock Input Ports
DCM Control and Data Input Ports
DCM Clock Output Ports
DCM Status and Data Output Ports
IBUFG – Global Clock Input Buffer
The DCM compensates for the clock input path when CLKFB is connected and an
IBUFG on the same half (top or bottom) of the device as the DCM is used.
BUFGCTRL – Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-5 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
PLL – Phase-Locked Loop
A PLL block within the same CMT can drive the CLKIN input of either DCM in the
CMT block. No global buffer is required in between. See
page 75
IBUF – Input Buffer
When an IBUF drives the CLKIN input, the PAD to DCM input skew is not
compensated.
Available Ports
for more information.
Table 2-3
www.xilinx.com
lists the available ports in the DCM_ADV primitive.
CLKIN, CLKFB, PSCLK, DCLK
RST, PSINCDEC, PSEN, DADDR[6:0], DI[15:0], DWE, DEN
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED, PSDONE, DO[15:0], DRDY
Port Names
Application Examples,
DCM Ports
51
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