XC6SLX150-3FGG484C Xilinx Inc, XC6SLX150-3FGG484C Datasheet - Page 26

• Manufacturer Part Number: XC6SLX150-3FGG484C
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX150-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 338
• Ram Bits: 4939776
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 338
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30
Table 30: Input Delay Measurement Methodology
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interface),
33 MHz and 66 MHz, 3.3V
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL, Class III
HSTL, Class I & II, 1.8V
HSTL, Class III 1.8V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
SSTL, Class II, 1.5V
LVDS (Low-Voltage Differential Signaling),
2.5V & 3.3V
LVPECL (Low-Voltage Positive Emitter-Coupled
Logic), 2.5V & 3.3V
BLVDS (Bus LVDS), 2.5V
Mini-LVDS, 2.5V & 3.3V
RSDS (Reduced Swing Differential Signaling),
2.5V & 3.3V
TMDS (Transition Minimized Differential Signaling),
3.3V
PPDS (Point-to-Point Differential Signaling,
2.5V & 3.3V
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the V
The value given is the differential input voltage.
shows the test setup parameters used for measuring input delay.
Description
L
and V
H
.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3, PCI66_3
HSTL_I, HSTL_II
HSTL_III
HSTL_I_18, HSTL_II_18
HSTL_III_18
SSTL3_I, SSTL3_II
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
SSTL15_II
LVDS_25, LVDS_33
LVPECL_25, LVPECL_33
BLVDS_25
MINI_LVDS_25,
MINI_LVDS_33
RSDS_25, RSDS_33
TMDS_33
PPDS_25, PPDS_33
I /O Standard Attribute
REF
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
REF
values. Reported delays reflect worst case of these measurements. V
/ V
MEAS
parameters found in IBIS models and/or noted in
1.25 – 0.125
V
V
1.3 – 0.125
1.2 – 0.125
V
V
V
V
V
V
1.25 – 0.1
REF
REF
1.2 – 0.3
1.2 – 0.1
3.0 – 0.1
REF
REF
REF
REF
REF
REF
V
L
0
0
0
0
0
0
– 0.75
– 0.75
(1)
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.2
Per PCI Specification
1.25 + 0.125
V
V
1.3 + 0.125
1.2 + 0.125
V
V
V
V
V
V
1.25 + 0.1
REF
REF
1.2 – 0.3
1.2 + 0.1
3.0 + 0.1
REF
REF
REF
REF
REF
REF
V
3.0
3.3
2.5
1.8
1.5
1.2
H
+ 0.75
+ 0.75
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.2
(1)
V
MEAS
Figure
V
V
V
V
V
V
V
V
1.65
1.25
0.75
0
0
0
0
0
0
0
1.4
0.9
0.6
REF
REF
REF
REF
REF
REF
REF
REF
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(3)(4)
4.
REF
V
REF
0.75
0.90
0.90
1.25
0.90
0.75
1.1
1.5
values
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(2)(4)
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