XC6SLX150-3FGG484C Xilinx Inc, XC6SLX150-3FGG484C Datasheet - Page 53

• Manufacturer Part Number: XC6SLX150-3FGG484C
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX150-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 338
• Ram Bits: 4939776
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 338
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter
CLKOUT_PER_JITT_FX
Duty Cycle
CLKOUT_DUTY_CYCLE_FX
Phase Alignment
CLKOUT_PHASE_FX
CLKOUT_PHASE_FX180
LOCKED Time
LOCK_FX
The values in this table are based on the operating conditions described in
For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on
the system application.
The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
Symbol
(2)
(4)(5)
(5)
(2)(3)
Frequency for the CLKFX and
CLKFX180 outputs
Period jitter at the CLKFX and
CLKFX180 outputs. When
CLKIN < 20 MHz
Period jitter at the CLKFX and
CLKFX180 outputs. When
CLKIN > 20 MHz
Duty cycle precision for the CLKFX
and CLKFX180 outputs including the
BUFGMUX and clock tree duty-cycle
distortion
Phase offset between the DFS
CLKFX output and the DLL CLK0
output when both the DFS and DLL
are used
Phase offset between the DFS
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
When 5 MHz < FCLKIN < 50 MHz,
the time from deassertion at the
DCM’s reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. When using both the DLL and
the DFS, use the longer locking time.
When FCLKIN > 50 MHz, the time
from deassertion at the DCM’s reset
input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and
CLKFX180 signals are valid. When
using both the DLL and the DFS, use
the longer locking time.
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2
Min
5
–
–
–
-3
Maximum = ±(1% of CLKFX period + 350)
Maximum = ±(1% of CLKFX period + 200)
and
±200
Max
0.45
375
Typical = ±(1% of CLKFX period + 100)
5
Table
Min
Use the Clocking Wizard
53.
5
–
–
–
-3N
Speed Grade
±200
Max
0.45
375
5
Min
5
–
–
–
-2
±200
Max
0.45
333
5
(1)
Min
5
–
–
–
-1L
±250
Max
0.60
200
5
Units
MHz
ms
ms
ps
ps
ps
ps
ps
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