XC6SLX150-3FGG484C Xilinx Inc, XC6SLX150-3FGG484C Datasheet - Page 74

• Manufacturer Part Number: XC6SLX150-3FGG484C
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX150-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 338
• Ram Bits: 4939776
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 338
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
The following table shows the revision history for this document.
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
06/24/09
08/26/09
01/04/10
02/22/10
03/10/10
Date
Version
1.0
1.1
1.2
1.3
1.4
Initial Xilinx release.
Added V
V
XC6SLX4 in
Table 24
values for T
to
T
(DRP) for DCM and PLL Before and After DCLK section from
Table
BUFIO2. Revised values for DCM_DELAY_STEP in
Table
Added -4 speed grade to entire document. Updated speed specification of -4, -3, -2 speed grades to
version 1.03. Added -1L speed grade numbers per speed specification 1.00. Updated T
Added -1L rows for LVCMOS12, LVCMOS15, and LVCMOS18 in
in
F
all parameters. Removed T
through
T
and XC6SLX75TCSG324; added XC6SLX75FG(G)484 and XC6SLX75FG(G)484.
Production release of XC6SLX16 -2 speed grade devices. The changes to
includes updating this data sheet to the data in ISE v11.5 software with speed specification v1.06.
Updated maximum of V
5, revised notes 1, 6, and 7, and added note 8 to R
data to I
V
I2C in
including adding values for PCI33_3. Updated V
missing V
and T
note 1 from
removed T
made typographical edits and removed notes. Removed clock CLK section in
CLK section and T
Updated values and added note 2 to
Numerous changes to
note 3 from
Production release of XC6SLX45 -2 speed grade devices, which includes changes to
Table 27
Fixed R
1 and the V, Max for TMDS_33 in
Also updated specifications for TMDS_33. Updated the
including adding values to
into
corrected some typographical errors and fixed SSO limits for bank1/3 in FG(G)484 package. Corrected
T
CLKFX_FREEZE_TEMP_SLOPE and added typical values to T
T
Table
OSCKC_OCE
SMCKCSO
MAX
LOCKMAX
CENTER_HIGH_SPREAD
BATT
CCO2
GTP Transceiver Specifications
Table 46, page 46
Table
in
RPW
50, added to F
53.
76, revised the XC6SLX16-CSG324 and the XC6SLX45-CSG484 and FG(G)484 values.
and I
Table
in
IN_TERM
RPU
Table
Table
FS
and added values to F
updating this data sheet to the data in ISE v11.5 software with speed specification v1.07.
Table
REF
9,
from
IODDO_T
note from
description, and changing the units of T
SUSPENDLOW_AWAKE
BATT
, I
to
Table
Table
9. Updated the description of
Table
Table
RPD
in
values in
43. Updated descriptions for T
Table
60. Added
6. Added
Table 34
Table
description in
in
, and I
36. Removed T
68. Added values to
REG_MUX
28,
Table
5. Updated
and added new tap parameters and note 2. In
1and
INMAX
including the addition of new values to various specifications, revising the
Table
37. In
Table
. Updated and added values to
Table
BATT
Table
IN
Table 7
1,
and
Table 49
Table
and V
www.xilinx.com
, revised F
Table
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
50. Updated note 3 in
, changed C
INITADDR
Table
Table
and T
30,
31. Added
46. Completely updated
Table
Table
Table
PCIEUSER
, T
2. Added R
TS
Table
and
16,
2, and
OSCCK_S
Table
REG_M31
55, updated CLKFX_FREEZE_VAR and
SUSPEND_ENABLE
(BUFPLL) and
in
and note 2 in
35. Also removed T
4. Added PCI66_3 to
from
Table
11. Removed DV
OUTMAX
Table 12
Description of Revisions
Table
Table
31, and
Table
IN
Simultaneously Switching Outputs, page
8. In
Table
. Added more networking applications to
, added R
Table 46
Table
17, and
and combinatorial section from
8. Removed PCI66_3 from
in
44. Added values to
FUSE
DNACLKL
, and removed PLL Maximum Output Frequency for
76. Added data to
Table
Table
through
4. Corrected the quiescent supply current for the
Table
11. Completely updated
REF
Table
to
FUSE
Table
Table 55
DT
and added new data. Updated values in
POR
Table 20
10, added note 1 to LVPECL_33 and TMDS_33.
, and T
Table
41. Added block RAM F
Table
value for HSTL_III_18 in
33. Updated note 3 on
and T
and R
Table
PPIN
. In
Table 61
Table
. Also, removed Dynamic Reconfiguration Port
1. In
DOQ
51. In
GTP Transceiver Specifications
2. Added XC6SLX75 and XC6SLX75T to
Table
Table 7
SCP_AWAKE
52. Updated CLKIN_FREQ_FX values in
from
DNACLKH
(DCM_CLKGEN). Removed
IN_TERM
55. Revised data in
Table
from
through
23. Added -2 data to
Table
Table 46
4, removed previous note 1 and added
Table 77
through
Figure
Table 45
CENTER_LOW_SPREAD
Table
and replaced note 1. Corrected note
Table
2, changed V
Table
, and added note 2 and 3. Updated
in
76: removed XC6SLX75CSG324
Table
in
Table 44
Table
2. Removed F
and updated all the notes. In
35. Removed T
9. Revised much of the detail
Table
Table
39,
and
Table
and removed note 1.
23. Added PCI66_3 back
Table
Table 26
MAX
Table
Table
Table
9. Updated PCI33_3 and
Table
Table
45. Numerous changes
75, and
IN
25. Updated
and revised values for
Table
values to
28. Removed T
37. In
, added I
Table
40, and
31. In
Table
40. Removed clock
78.
30. Updates
and
PCIECORE
60. Removed
Table 26
and
Table
SOL
ISDO_DO
Table
25. Updated
25. Updated
section
Table
Table 27
IN
Table
Table
in
Table 47
and note
Table 28
78. In
38,
Table
33,
and
from
and
GSRQ
42.
41,
1.
74