XC6SLX150-3FGG484C Xilinx Inc, XC6SLX150-3FGG484C Datasheet - Page 75

• Manufacturer Part Number: XC6SLX150-3FGG484C
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX150-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 338
• Ram Bits: 4939776
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 338
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS162 (v2.0) March 31, 2011
Preliminary Product Specification
06/14/10
06/24/10
07/16/10
07/26/10
08/23/10
11/05/10
Date
Version
1.10
1.5
1.6
1.7
1.8
1.9
In
delineation, revised I
DIFF_MOBILE_DDR to
Table
descriptions and added data to
Applications section in
speed specification v1.08. In
Updated the maximum I/O pairs per bank in
in
value, added T
F
on the XC6SLX45-FG(G)676 and revised the XC6SLX45T and XC6SLX150T values.
The following changes to this specification are addressed in the product change notice
XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs.
In
specifications. In
specifications for the memory controller block and note 2. Added Note 4 and updated values in
Table
Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed
grade) devices which includes changes to
specification v1.08).
Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB functionality
(specifications are identical to the -3 speed grade). This includes changes to
(note 4), and
Updated
F
speed grade) values. In
spread spectrum section of
Production release of specific devices listed in
speed specification v1.11. Added note 4 advising designers of the patch which contains v1.11. Also
updated the -1L speed specification to v1.04. Updated numerous -4 and -1L values. Added -4 T
values and F
Table
Production release of XC6SLX25, XC6SLX25T, XC6SLX100 and XC6SLX100T in the specific speed
grades listed in
note 7 to
note 1 to
Table
CLKIN_CLKFB_PHASE and CLKOUT_PHASE_DLL values. Updated note 3 in both
Table
Updated values for F
Table
Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in
Table 27
the 12.3 Speed Files Patch. Added Note 3 advising designers of the patch which contains v1.12.
In
added Note 2. In
T
redefined and expanded description for CLKIN_FREQ_DLL and rewrote Note 3. Updated title of
Table
of T
For the -1L speed grade, updated data sheet to ISE 12.3 software with speed specification v1.05 which
revised the values in the following tables:
through
Updated
RBCCK
MINCAL
USERCCLKH
Table
Table
Table
Table
PSFD
16. Updated F
33.
41, revised T
46. In
55.
21. Removed the -1L speed grade readback support restriction and Note 3 in
56. Also in
. Updated and added data to
Table
2, added note 5 and added temperature range to V
43. In
2, revised the V
2, added Note 4. In
/ T
values in
Table 2
using ISE v12.3 software with speed specification v1.12 for the -2 speed grade available in
Simultaneously Switching Outputs
Notice of
Table
PHFD
Table
MINCAL
and T
Switching Characteristics (Table
42,
Table
BPIICCK
Table 26
28. Added and updated SSO limits per V
and moved V
Table
in
Table
Table
Table 47
52, removed -1L specifications for CLKOUT_PER_JITT_DV1/2 and revised
Table
USERCCLKL
Disclaimer.
REG
Table
GTPDRPCLK
to
46, updated description for T
RPD
GTPRANGE1
Table
and T
Table
. Added new -1L values to
75, revised T
25, changed the standard specifications and added extended performance
46, updated symbol for T
Table 8
Table
CCINT
38. In
and
description, and updated note 2 in
68.
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
through
Table
Table
SPIICCK
25. Updated
Table
38. Revised T
Table 27
FS
47, updated T
, and added and revised the modes for F
to add the memory controller block extended performance
Table
Table
and
in
, F
and R
55.
4, added Note 2. In
Table
GTPRANGE2
28, added DIFF_MOBILE_DDR and updated -4 speed grade data.
Table
DCD_CLK
. Also in
Table
Table 61
39, updated T
Description of Revisions
23. Removed note 1 and added new data to the Networking
using ISE v12.2 software with speed specification v1.11. Added
FUSE
19. Increased maximum T
Table 26
Table
54,
10. Added note 4 to
Table 26
CINCK
discussion. Added -3 speed grade values for T
GIO
to a new
Table
Table
for XC6SLX150 and XC6SLX150T. Changed description
Table 60
through
, and F
26).
Table 26
25,
(-2 and -3 speed grade) values. Updated -3 values in
SMWCCK
/T
SMCKCSO
Table
32. Updated note 2 on
and
46, added device dependencies to F
CKCIN
RPW
Table
and
Table
GPLLMIN
Table
Table
through
Table 27
(-2 and -3 speed grade) values and F
46. Added and updated values in
Table 27
and
CCO
/T
in
28,
, revised values for T
SMCCKW
3. Added I
Table
FS
75, and
Table
/GND pairs in
10, added Notes 2 and 3. In
Table 27
Table
in
Table
and R
Table
Table
to the data in ISE v12.1 software with
39. In
(ISE v12.1 software with speed
4. Added note 2 to
LLSKEW
34,
, changed -1L values for
Table
15. Changed minimum DV
FUSE
75,
HS
using ISE v12.2 software with
18. Revised -3 and -4 values in
MCCK
Table
Table
and Note 4 to
Table
Table
. Removed speed grade
78. In
in
Table
Table 2
and F
35,
Table
40, revised T
77, and
38. Revised the F
POR
Table
33. Added note 3 to
Table
SMCCK
22. Updated
(note 2),
Table
and added Min
Table 54
Table 26
Table
76, added data
Table
36,
Table
SMCCK
. In
Table
Table
46.
Table 39
SHCKO
TAP
7. Added
Table
4. Added
Table 25
78.
TOG
and
and
PPIN
and
and
43,
76.
TAP
MAX
. In
(-3
51,
in
75