XC6SLX150-3FGG484C Xilinx Inc, XC6SLX150-3FGG484C Datasheet - Page 37

• Manufacturer Part Number: XC6SLX150-3FGG484C
• Description: FPGA Spartan®-6 Family 147443 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX150-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 147443
• Device Logic Units: 92152
• Number Of Registers: 184304
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 338
• Ram Bits: 4939776
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 338
• Number Of Logic Elements/cells: 147443
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input/Output Logic Switching Characteristics
Table 34: ILOGIC2 Switching Characteristics
Table 35: OLOGIC2 Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Setup/Hold
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
Setup/Hold
T
T
T
T
T
Sequential Delays
T
T
ICE0CK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
RQ_ILOGIC2
ODCK
OOCECK
OSRCK
OTCK
OTCECK
OCKQ
RQ_OLOGIC2
/T
/T
/T
Symbol
/T
/T
Symbol
/T
OCKT
/T
OCKD
/T
ICKSR
IOCKD
/T
OCKSR
ICKCE0
IOCKDD
OCKTCE
OCKOCE
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
CLK to OQ/TQ out
SR pin to OQ/TQ out
CE0 pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY2)
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY2)
D pin to Q pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2)
CLK to Q outputs
SR pin to Q outputs
Description
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
–0.05
–0.10
–0.28
–0.08
–0.06
–0.30
–0.23
–0.83
0.81
0.75
0.70
0.24
0.58
0.48
1.81
0.56
0.74
1.19
0.31
0.00
0.95
0.23
1.56
0.68
1.03
1.81
-3
-3
–0.05
–0.10
–0.28
–0.06
–0.06
–0.25
–0.22
–0.83
Speed Grade
Speed Grade
0.86
0.75
0.79
0.56
0.72
0.51
1.81
0.56
0.74
1.36
0.47
0.00
1.28
0.39
1.86
0.97
1.24
1.81
-3N
-3N
–0.05
–0.23
–0.01
–0.01
–0.22
–0.20
–0.83
1.18
0.00
1.01
1.03
0.83
1.18
0.74
2.50
0.79
0.98
1.73
0.54
0.00
1.53
0.44
2.39
1.20
1.43
2.50
-2
-2
–0.27
–0.23
–0.47
–0.19
–0.13
–0.52
–0.45
–1.77
–0.39
1.73
1.66
1.39
0.99
1.51
0.68
3.05
1.94
1.21
1.31
2.18
0.63
2.25
0.74
3.49
2.11
3.05
-1L
-1L
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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