ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 23

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
Table 11.
Table 12.
ISP1508A_ISP1508B_1
Product data sheet
Signal
TX_ENABLE
TX_DAT
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
Reserved
Signal
TX_ENABLE
DAT
Signal mapping for 6-pin serial mode
Signal mapping for 3-pin serial mode
9.2.3 6-pin full-speed or low-speed serial mode
9.2.4 3-pin full-speed or low-speed serial mode
Maps to
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Maps to
DATA0
DATA1
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1508 to 6-pin serial mode. In 6-pin serial mode, the data bus
definition changes to that shown in
6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial
mode, the link asserts the STP signal. This is provided primarily for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1 before entering 6-pin serial mode.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
The 6-pin serial mode is not applicable if the ISP1508 functions as a 4-bit DDR.
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1508 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in
3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial
mode, the link asserts the STP signal. This is provided primarily for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1 before entering 3-pin serial mode.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
Direction
I
I
I
O
O
O
O
O
Direction
I
I/O
Rev. 01 — 14 August 2007
Description
active HIGH transmit enable
transmit differential data on DP and DM
transmit single-ended zero on DP and DM
active HIGH interrupt indication; will be asserted and latched whenever
any unmasked interrupt occurs
single-ended receive data from DP
single-ended receive data from DM
differential receive data from DP and DM
reserved; the ISP1508 will drive this pin to LOW
Description
active HIGH transmit enable
transmit differential data on DP and DM when TX_ENABLE is HIGH
receive differential data from DP and DM when TX_ENABLE is LOW
Table
Table
11. To enter 6-pin serial mode, the link sets the
12. To enter 3-pin serial mode, the link sets the
ISP1508A; ISP1508B
ULPI HS USB transceiver
© NXP B.V. 2007. All rights reserved.
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