TDA18271HD/C2-T NXP Semiconductors, TDA18271HD/C2-T Datasheet - Page 19

• Manufacturer Part Number: TDA18271HD/C2-T
• Description: Tuners HYBRIDE
• Manufacturer: NXP Semiconductors

Specifications of TDA18271HD/C2-T

• Bus Type: I2C
• Maximum Agc: 71 dB
• Maximum Frequency: 864 MHz
• Minimum Frequency: 45 MHz
• Mounting Style: SMD/SMT
• Package / Case: HLQFN-64
• Function: TV
• Noise Figure: 5.5 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.13 V
• Supply Voltage (max): 3.47 V
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA18271HD/C2,518

NXP Semiconductors
Table 24.
Legend: * power-on reset value.
TDA18271HD_4
Product data sheet
Address
10h
11h
12h
EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description
Register
EB1
EB2
EB3
9.3.12 Description of Main post-divider byte
9.3.13 Description of Main divider bytes 1, 2 and 3
9.3.14 Description of Extended bytes 1 to 23
Table 22.
Legend: * power-on reset value.
Table 23.
Legend: * power-on reset value.
Bit
7 to 3
2
1
0
7 to 0
7 to 0
Bit
7
6 to 0
Address Register Bit
0Dh
0Eh
0Fh
Symbol
IF_NOTCH
MAIN_POST_DIV[6:0]
Symbol
EB1[7:3]
CALVCO_FORLON R
AGC1_ALWAYS_
MASTERN
AGC1_FIRSTN
EB2[7:0]
EB3[7:0]
MD1
MD2
MD3
MPD - Main post-divider byte (subaddress 0Ch) bit description
MD1, MD2 and MD3 - Main divider bytes 1, 2 and 3 (address 0Dh, 0Eh and 0Fh) bit
description
7
6 to 0 MAIN_DIV[22:16] R/W
7 to 0 MAIN_DIV[15:8]
7 to 0 MAIN_DIV[7:0]
Rev. 04 — 19 May 2009
Symbol
-
Access
R
R
R
R/W
R/W
Access
R/W
R/W
Value
1 1111*
1*
0
1*
0
1*
0
0000 0001*
1000 0100*
Value
0*
000
Access Value Description
R/W
R/W
R/W
0*
00h*
00h*
00h*
Description
extended byte 1
determines VCO used during Normal
mode operations
enables AGC1 normal operation
whatever the tuner type (master or
slave)
determines which AGC will be updated
when detectors 1 and 2 are active
extended byte 2
extended byte 3
Description
adds a DC notch in IF for better
adjacent channels rejection; depends
on standards; see
LO synthesizer post-divider; see
Table 47
LO VCO is used
CAL VCO is used
normal operation for the master;
6 dB fixed for the slave
normal operation for both the master
and the slave
AGC1 and AGC2 both updated
AGC1 has priority on AGC2
must be set to 0
LO synthesizer main divider bits
TDA18271HD
© NXP B.V. 2009. All rights reserved.
Table 43
Silicon Tuner IC
19 of 70