STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 24

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
III.7.4.3 - Memory obtained with 8M x 8 SDRAM
circuit
The Address bits delivered by the Multi-HDLC for
8M x 8 SDRAM microprocessor circuits are:
– ADM12/13 for Bank select corresponding with
– ADM0/11 for Row address inputs corresponding
– ADM0/8 for Column address inputs correspond-
III.7.4.4 - Memory obtained with 4M x 16
SDRAM circuit
The Address bits delivered by the Multi-HDLC for
4M x 16 SDRAM circuits are:
– ADM12/13 for Bank select corresponding with
– ADM0/11 for Row address inputs corresponding
– ADM0/7 for Column address inputs correspond-
III.8 - Bus Arbitration
The Bus arbitration function arbitrates the access
to the bus between different entities of the circuit.
Those entities which can call for the bus are the
following:
– The receive DMA controller,
– The microprocessor,
– The transmit DMA controller,
– The Interrupt controller,
– The memory interface for refreshing the
This list gives the memory access priorities per de-
fault.
If the treatment of more than 64 HDLC channels is
required by the application, it is possible to chain
several Multi-HDLC components. That is done
with two external pins (TRI, TRO) and a token ring
system.
The TRI, TRO signals are managed by the bus ar-
bitration function too. When a chip has finished its
tasks, it sends a pulse of 30 ns to the next chip.
24/130
Signals
NCE1
NCE0
A22/23 delivered by the microprocessor
with A10/21 delivered by the microprocessor
ing with A1/9 delivered by the microprocessor
A21/22 delivered by the microprocessor
with A9/20 delivered by the microprocessor
ing with A1/8 delivered by the microprocessor
SDRAM.
Signals
UDQM
LDQM
A23
1
0
A0 or equivalent
Signals
UDQM
LDQM
1
0
equiva-
A0 or
lent
NLDS
1
0
0
1
NLDS NUDS
0
1
NUDS
1
0
1
0
III.9 - Clocks
III.9.1 - Clock Distribution Selection and Super-
vision
Two clock distributions are available:
Clock at 4.096 MHz or 8.192 MHz and a synchro-
nization signal at 8 KHz.
The component has to select one of these two dis-
tributions and to check its integrity.
Two other clock distributions are allowed: Clock at
3072 MHz or 6144 MHz and a synchronization sig-
nal at 8 KHz.
See General Configuration Register GCR (02)
DCLK, FSC GCI and FSC V* are output on three
external pins of the Multi-HDLC. DCLK is the clock
selected between Clock A and Clock B. FSC, GCI
and FSC V* are functions of the selected distribu-
tion and respect the GCI and V* frame synchroni-
zation specifications.
The supervision of the clock distribution consists
of verifying its availability. The detection of the
clock absence is done in a less than 250 microsec-
onds. In case the clock is absent, an interrupt is
generated with a 4 kHz recurrence. Then the clock
distribution is switched automatically up to detec-
tion of couple A or couple B. When a couple is de-
tected the change of clock occurs on a falling edge
of the new selected distribution. Moreover the
clock distribution can be controlled by the micro-
processor thanks to SELB, bit of General Configu-
ration Register.
Depending on the applications, three different sig-
nals of synchronization (GCI, V* or Sy) can be pro-
vided to the component. The clock A/B frequency
can be a 4096 or 8192 kHz clock. The component
is informed of the synchronization and clocks that
are connected by software.
III.9.2 - VCXO Frequency Synchronization
An external VCXO can be used to provide a clock
to the transmission components. This clock is con-
trolled by the main clock distribution (Clock A or
Clock B at 4096kHz). As the clock of the transmis-
sion component is 15360 or 16384kHz, a config-
urable function is necessary.
The VCXO frequency is divided by P (30 or 32) to
provide a common sub-multiple (512kHz) of the
reference
(4096kHz). The comparison of these two signals
gives an error signal which commands the VCXO.
Two external pins are needed to perform this func-
tion: VCXO-IN and VCXO-OUT.
frequency
CLOCKA
or
CLOCKB
H
.