FW82371EB Intel, FW82371EB Datasheet - Page 22

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
9.
Problem:
Implication: The 440BX host controller will delay transaction (retry) a PC/PCI ISA master cycle (PIIX4 DMA
Workaround: None.
Status:
10.
Problem:
Implication: In Bus Master IDE (BMIDE) mode, the PCI interface is prefetching data. If this prefetched data gets
Workaround: If the controller locks up, the BMIDE driver must timeout, reset the PIIX4 Start/Stop Bus Master bit, and
Status:
11.
Problem:
Implication: This failure only occurs when some PCI devices introduce large (>15usec) latencies on the PCI bus in
Workaround: In all cases found to date, the software drivers of the PCI devices causing large delays can be modified to
Status:
22
®
82371EB (PIIX4E)
PCI Arbiter Advances when PC/PCI ISA Master Gets Retried by the Host
Controller
When a PC/PCI ISA master cycle gets retried (delayed transaction) by the host controller, the PIIX4 PCI
Arbiter advances to a pending PCI master (USB or IDE). Affects 440BX-PIIX4-MoonISA Docking
platforms.
controller in cascade mode) from PCI to DRAM. When the PIIX4 detects the retry, it will do a passive
release on the PHLD# signal and allow another PCI master (440BX Arbiter) to acquire the bus.
Following the passive release, the PIIX4 will un-intentionally advance its PCI arbiter to a pending PCI
master request (USB or IDE). The 440BX expects to the next cycle from PIIX4 to be the delayed
transaction cycle and will retry any other cycle (USB or IDE). The PIIX4 arbiter will stay on the USB or
IDE bus master device until the delay transaction timeout in the 440BX. After the timeout the 440BX
drops the data possibly resulting in a system hang.
This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the
specification.
Bus Master IDE Timeout
During an IDE DMA write, the PIIX4 IDE controller will invalidate its FIFO if the IDE device deasserts
its DREQ signal for greater than 1us. During the FIFO invalidation, the PIIX4 does not prevent a FIFO
fill from PCI.
inserted into the IDE FIFO (during a FIFO invalidation due to DREQ deassertion > 1us) the IDE
controller will lock up. Any future reassertion of the DREQ signal will not be acknowledged by the
PIIX4 IDE controller. BMIDE transactions will not complete on either the primary or secondary channel.
retry the transfer. Note that this errata does not occur using PIO mode or Ultra DMA/33 mode.
This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the
specification.
USB-PCI Latency
Under certain circumstances, PIIX4 will start an isochronous USB transfer when there is not enough time
to successfully complete the transaction.
combination with the USB transfer. In this situation, the USB port shuts down and requires the user to
unplug the device, then plug it back in to get the device operational again. The rest of the system will
continue to operate normally.
reduce the latency to less than 15usec. When the PCI delays are reduced to this level the isochronous
USB transfers will operate normally.
There are currently no plans to fix this erratum.
Specification Update
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