FW82371EB Intel, FW82371EB Datasheet - Page 28

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
Specification Clarifications
1.
2.
28
®
82371EB (PIIX4E)
SUSA#, SUSB#, and SUSC# State transition during RESET
After a hard reset (a write to C9h bit 2, with bit 1 set to 1) SUSA#, SUSC# immediately transition low
for three to four RTC clocks.
In many system designs, these signals control the various power plans. If the assertion of these signals
do not affect the state of PWROK from the power supply circuitry, the hard reset completes normally
with a system reboot. If the assertion of these signals cause the power supply circuitry to deassert
PWROK, the PIIX4 will reset and power-up the system like it was performing a cold boot. In both cases
the system reboots.
This clarification applies to all steppings of the PIIX4 and will be incorporated into the next revision of
the PIIX4 datasheet.
CONFIG[1] Definition
CONFIG[1]
In addition to controlling the polarity of INIT and CPURST, this signal also controls the latching of
NMI, SMI#, INTR, and INIT. In a Pentium Processor based system (CONFIG[1]=0) NMI, SMI#,
INTR, and INIT flow unlatched to the processor in all power managed states. In a Pentium Pro
Processor based system (CONFIG[1]=1) NMI, SMI#, INTR, and INIT will be latched when
STPCLK# is asserted, and held for 5 PCICLKs after STPCLK# is deasserted.
This clarification applies to all steppings of the PIIX4 and will be incorporated into the next revision
of the PIIX4 datasheet.
2.1.12 Other System and Test Signals
Name
Type
I
CONFIGURATION SELECT 1:
This input signal is used to select the type of microprocessor is being
used in the system. If CONFIG[1] = 0, the system contains a
Pentium microprocessor. If CONFIG[1] = 1, the system contains a
Pentium Pro microprocessor. CONFIG[1] is used to control the
polarity of the INIT and CPURST signals and the latching of NMI,
SMI#, INTR, and INIT. If CONFIG[1]=1, INIT# and CPURST# are
active low and NMI, SMI#, INTR, INIT# flow unlatched to the
processor. If CONFIG[1]=0, INIT and CPURST and active high and
NMI, SMI#, INTR, and INIT will be latched when STPCLK# is
asserted, and held for 5 PCICLKs after STPCLK# is deasserted.
Description
Specification Update
R