FW82371EB Intel, FW82371EB Datasheet - Page 42

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

5.
6.
7.
8.
9.
10.
PIO0 Timing Values
Table 14 in the PIIX4 Datasheet incorrectly lists the PIO0 cycle time, IORDY Sample Point and
Recovery Time. The IORDY sample time is 6 clocks, the Recovery Time is 14 clocks, the 30 MHz
cycle time is 660 Ns and the 33 MHz cycle time is 600 Ns.
This change applies to all steppings of the PIIX4 and will be incorporated into the next revision of the
PIIX4 datasheet.
Table 1. DMA/PIO Timing Values (Based on PIIX4 Cable Mode and System Speed)
Table 50 STD to ON is Max Value
STD to ON Timings, tl38, shown in table 50 of page 257 is mistakenly indicated as a Min value. T138
of STD to On is a Max value.
Fast_A20
The description of the Fast_A20 bit indicates a value of 1 causes A20M# to assert to 0. The correct
description should be 1=Causes A20M# signal to be deasserted to 1. The table in the description is
correct.
Sleep and Deep Sleep for Pentium® II Processors Only
The PIIX4 Datasheet, section 11.2.1, identifies Stop Clock State and Deep Sleep State as being available
for Pentium® II processors only, which is incorrect.
The Sleep State and the Deep Sleep State are for Pentium® II processors only, the Stop Clock State is
available for all CPU types.
SMI# Minimum Deassertion
The PIIX4 Datasheet Addendum in Table 5 and Figure 5 show SMI# deassertion minimum width as 4
PCI Clocks. The correct minimum deassertion time is 1 PCI Clock, as would be observed on back to
back SMI’s. The PIIX4 Datasheet correctly identifies the minimum deassertion time as 1 PCI Clock.
Datasheet t37 Correction
The PIIX4 Datasheet, Figure 23 and Table 43, show t37 (SUS_STAT[1:2]# Active to CPU_STP# and
PCI_STP# Active) as 1 RTC Clock Max. The actual timing is 1 RTC Clock Minimum.
PIO0/
Compatible
PIIX4 Drive
Mode
Point (ISP)
6 clocks
(default)
Sample
IORDY
Time (RCT)
Recovery
14 clocks
(default)
IDETIM[15:8]
Attached
(Master)
If Slave
Drive 0
C0h
IDETIM[15:8]
attached or
If no Slave
(Master)
Mode 0
Slave is
Drive 0
80h
1
SIDETIM
Sec{7:4]
Pri[3:0]
Drive 1
(Slave)
0
30 MHz: 660ns
33 MHz: 600ns
frequency and
Cycle Time
cycle time.
Resultant
operating
Base