FW82371EB Intel, FW82371EB Datasheet - Page 38

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
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82371EB (PIIX4E)
The SMBus controller will not respond to the START bit being set unless all interrupt status bits in the
SMBHSTSTS register have been cleared.
For Block Read or Block Write protocols, the data is stored in a 32-byte block data storage array. This
array is addressed via an internal index pointer. The index pointer is initialized to zero on each read of
the SMBHSTCNT register. After each access to the SMBBLKDAT register, the index pointer is
incremented by one. For Block Write transactions, the data to be transferred is stored in this array and
the byte count is stored in SMBHSTDAT0 register prior to initiating the transaction. For Block Read
transactions, the SMBus peripheral determines the amount of data transferred. After the transaction
completes, the byte count transferred is located in SMBHSTDAT0 register and data is stored in the block
data storage array. Accesses to the array during execution of the SMBus transaction always start at
address 0.
Any register values needed for computation purposes should be saved prior to the starting of a new
transaction, as the SMBus host controller updates the registers while executing the new transaction.
GPI14 for Device 5 Can Cause IO Trap SMI#
Page 219 of the datasheet, section 11.3.5.6 describes how the PIIX4 will respond to GPI14 for Device 5
system events. The 3
low) is selectable. This can cause idle, burst, or global standby timer reloads.”
This bullet is changed to “ Assertion of GPI14. The polarity of active signal (high or low) is selectable.
This can cause idle, burst, global standby timer reloads, or IO Trap SMI#.”
XDIR# Assertion
Page 22 of the datasheet, section 2.1.3, describes the XDIR# signal. The second sentence of the
description, “XDIR# is asserted (driven low) for all I/O read cycles regardless if the accesses is to a
PIIX4 supported device.” should be changed to “XDIR# is asserted (driven low) for all I/O read cycles
targeting the XBUS or enabled Generic Decode Chip Selects.”
Correction to the USB Bandwidth Reclamation Errata Workaround
The workaround for the USB Bandwidth Reclamation Errata workaround is not correctly documented in
Errata number 4. The following changes are required.
1) The Queue Head Link Pointer must be set to point to the next Queue Head, not the pseudo TD as
2) The Queue Head Link Element Pointer (DW 04-07h) must be set to point to the Pseudo TD.
Do Not Use 4-Clock Serial IRQ Start Frame Width When CLKRUN# is Enabled
When a device wants to start a serial IRQ cycle in Quiet Mode, it will drive the SERIRQ line low for one
clock, and then tristate the line. The PIIX4 will then begin driving SERIRQ low so that it will be held
low for a total of 4, 6, or 8 clocks. This Serial IRQ Start Frame pulse width is programmable, via
Function 0 offset 64h, SERIRQC[1:0]. The requesting device must see SERIRQ low for at least 4 clocks.
In cases where incorrect CLKRUN# protocol is implemented, interrupting clocks, the requesting device
may not see 4 clocks of low time. An example of this is when CLKRUN# may be reasserted by a PCI
agent too late to guarantee uninterrupted clocks, but before the clock actually stops. This will result in a
failed SERIRQ cycle. When CLKRUN# protocol is implemented in a PIIX4 system, setting the Serial
IRQ Start Frame pulse width to 6 or 8 clocks will make the PIIX4 immune from this condition.
indicated.
rd
bullet currently states “ Assertion of GPI14. The polarity of active signal (high or
Specification Update
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