MT46V128M8P-6T:A Micron Technology Inc, MT46V128M8P-6T:A Datasheet
MT46V128M8P-6T:A
Specifications of MT46V128M8P-6T:A
Related parts for MT46V128M8P-6T:A
MT46V128M8P-6T:A Summary of contents
Page 1
... Notes: 1. Not recommended for new designs. t RCD) Clock Rate (MHz 2 167 200 167 n/a 133 n/a 1 1Gb: x4, x8, x16 DDR SDRAM (400-mil width, 0.65mm pin pitch) (400-mil width, 0.65mm pin pitch See Table 3 on page 2 for module compatibility. Data-Out Access Window Window 1.6ns ±0.70ns 2.0ns ± ...
Page 2
... IT Special Options TG P Speed Grade 5ns - 6ns 2.5 - 7.5ns 2.5 -75 2 1Gb: x4, x8, x16 DDR SDRAM 128 Meg Meg Meg banks 8K 16K (A0–A13) 16K (A0–A13) 4 (BA0, BA1) 4 (BA0, BA1) 2K (A0–A9, A11) 1K (A0–A9) Yes Yes Yes Yes – ...
Page 3
... SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Power-down (CKE Not Active .81 PDF: 09005aef80a2f898/Source: 09005aef82a95a3a 1Gb_DDRTOC.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN 1Gb: x4, x8, x16 DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2003 Micron Technology, Inc. All rights reserved. Table of Contents ...
Page 4
... BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 1Gb: x4, x8, x16 DDR SDRAM State Diagram Self refresh REFS REFSX Idle REFA ...
Page 5
... READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access ...
Page 6
... Functional Block Diagrams The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits internally configured as a 4-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram CKE CK# CK Control CS# logic WE# CAS# RAS# Refresh 13 counter Mode registers 16 14 A0–A13, ...
Page 7
... DM mask logic Bank control logic 2 512 Column decoder Column- 9 address 10 counter/ latch 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 1Gb: x4, x8, x16 DDR SDRAM Functional Block Diagrams Bank 3 DLL Data READ MUX latch DRVRS 8 1 DQS generator Column 0 ...
Page 8
... WE# WE# 21 CAS# CAS# 22 RAS# RAS# 23 CS# CS BA0 BA0 26 BA1 BA1 27 A10/AP A10/ Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions x16 DQ7 NF 65 DQ15 DQ14 63 DQ6 DQ3 62 DQ13 ...
Page 9
... Supply DQ power supply: Isolated on the die for improved noise immunity. Micron Technology, Inc., reserves the right to change products or specifications without notice. 9 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions is applied and until CKE is first brought DD ©2003 Micron Technology, Inc. All rights reserved. ...
Page 10
... No function for x4: These pins should be left unconnected. – Do not use: Must float to minimize noise on V Micron Technology, Inc., reserves the right to change products or specifications without notice. 10 1Gb: x4, x8, x16 DDR SDRAM Pin Assignments and Descriptions . REF ©2003 Micron Technology, Inc. All rights reserved. ...
Page 11
... MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 11 1Gb: x4, x8, x16 DDR SDRAM Package Dimensions Gage plane +0.10 –0.05 Detail A ©2003 Micron Technology, Inc. All rights reserved. 0.25 0.80 TYP ...
Page 12
... CK (MIN); DQ, DM REFC = RFC (MIN REFC = 7.8µ Standard Micron Technology, Inc., reserves the right to change products or specifications without notice. 12 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6T, -75); DD -5B -6T -75 Units 165 160 145 mA 200 195 180 ...
Page 13
... I 4R Continuous burst 0mA OUT (MIN); DQ, DM REFC = RFC (MIN REFC = 7.8µ Standard 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – +2.5V ±0.2V (-6T, -75); DD -5B -6T -75 170 165 145 215 210 195 280 270 245 285 275 250 345 340 ...
Page 14
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 14 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – RFC REFI CL 9 n/a n/a n/a 10 n/a n/a n/a 11 n/a n/a n/a 9 n/a n/a 2 ...
Page 15
... OL , REF ) OHR OUT Q - 0.373V, minimum , minimum OLR OUT , REF ) 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Min Max –1V +3.6V –1V +3.6V –1V +3.6V –0. 0.5V DD –55 +150 – +2.6V ±0.1V Min Max Units +2.5 +2.7 +2.5 +2.7 0.49 × 0.51 × ...
Page 16
... I OLR OUT , REF ) +2.5V ±0.2V +2.5V ±0. Symbol REF AC 16 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and +2.5V ±0.2V Min Max +2.3 +2.7 +2.3 +2.7 0.49 × 0.51 × 0. 0.04 REF REF 0.3 REF DD –0 0.15 REF – ...
Page 17
... V TT 25Ω Reference 25Ω point Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Receiver ©2003 Micron Technology, Inc. All rights reserved ...
Page 18
... Q = +2.5V ±0.2V +2.5V ±0. Symbol 0.5 × MIN when static and is centered around 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and +2.6V ±0.1V +2.6V ±0.1V for -5B Min Max 1.15 1.35 –0 0 0 0.2 0.5 × 0 Maximum clock level Minimum clock level ...
Page 19
... Delta input capacitance: CK, CK# Input/output capacitance: DQ, LDQS, UDQS, LDM, UDM Input capacitance: Command and address Input capacitance: CK, CK# Input capacitance: CKE PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC Symbol Min DC – – ...
Page 20
... QHS t RAP t RAS RCD t 1Gb REFC t 1Gb RFC t REFI 1Gb RPRE t RPST t RRD t VTD t WPRE t WPRES t WPST 20 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units –0.70 +0. 0. 0.45 0.55 CK 0.40 – ns 1.75 – ns –0.60 +0. ...
Page 21
... Data valid output window PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ +2.6V ±0.1V +2.6V ±0.1V DD Symbol WTR t XSNR 1Gb t XSRD n/a 21 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -5B Min Max Units 15 – – CK 126 – 200 – ...
Page 22
... RAS t t RCD t REFC 1Gb t 1Gb REFI t 1Gb RFC t t RPRE t RPST t RRD t VTD t WPRE t WPRES 22 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units AC –0.70 +0. 0. 0.45 0.55 DH 0.45 – 1.75 – –0.6 +0 ...
Page 23
... PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ +2.5V ±0.2V +2.5V ±0.2V DD Symbol t WPST t t WTR t XSNR 1Gb t XSRD n/a 23 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -6T (TSOP) Min Max Units t 0.4 0 – – 126 – t 200 – ...
Page 24
... DQS write preamble setup time DQS write postamble PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ +2.5V ±0.2V +2.5V ±0. 2 1Gb 1Gb 1Gb 24 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Symbol Min Max Units t AC –0.75 +0. ...
Page 25
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ +2.5V ±0.2V +2.5V ±0.2V DD 1Gb Q = +2.5V ±0.2V +2.5V ±0. 1.00 1.05 1. +2.5V ±0.2V +2.5V ±0. 0.50 0.55 0.60 25 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -75 Symbol Min Max Units – t WTR 1 – t XSNR 127.5 – t XSRD 200 – ...
Page 26
... Specified values are obtained specifications are tested after the device is properly initialized and is averaged at = +2.5V ±0.2V 25° OUT 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC -to-V swing 1.5V in the test environ- IH (or to the crossing point for CK/CK#), REF ( ) and ...
Page 27
... DDR). However, an AUTO REFRESH command must be asserted at least once every 70.3µs (140.6µs for 128Mb DDR); burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device ...
Page 28
... V-I curve of Figure 11 on page 29. and voltage will lie within the outer bounding lines of the V-I curve of Figure 12 on page 29. 28 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC - 7.5ns -75E / - 7.5ns - 6ns ...
Page 29
... V-I curve of Figure 13 on page 30. and voltage will lie within the outer bounding lines of the V-I curve of Figure 14. 29 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2 ...
Page 30
... V Q must track each other DQSCK (MAX DQSCK (MIN) + RPRE (MAX) condition. 30 1Gb: x4, x8, x16 DDR SDRAM Electrical Specifications – DC and AC 2.0 2.5 2.0 2.5 level and the referenced test DD pulse width ≤ 3ns, and the pulse t RPST (MAX) condition. ...
Page 31
... Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ± ...
Page 32
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 1Gb: x4, x8, x16 DDR SDRAM Pull-Up Current (mA) Nominal High Min Max –7.6 –4.6 –10.0 –14.5 –9.2 –20.0 –21.2 –13.8 – ...
Page 33
... Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 1Gb: x4, x8, x16 DDR SDRAM Pull-Up Current (mA) Nominal High Min Max –4.3 –2.6 –5.0 –7.8 –5.2 –9.9 –12.0 –7.8 – ...
Page 34
... Table 23: Truth Table 2 – DM Operation Used to mask write data, provided coincident with the corresponding data Name (Function) Write enable Write inhibit PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN 1Gb: x4, x8, x16 DDR SDRAM CS# RAS# CAS# WE ...
Page 35
... Once RFC is met, the DDR SDRAM will be in the all banks idle state. 35 1Gb: x4, x8, x16 DDR SDRAM is HIGH (see Table 27 on page 38) and has been met ...
Page 36
... PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ MRD has been met. Once MRD is met, the DDR SDRAM will be in the all banks idle state met. Once RP is met, all banks will be in the idle state. ...
Page 37
... The minimum delay from a READ or WRITE command with auto precharge enabled command to a different bank is summarized in Table 26. To Command PRECHARGE ACTIVE PRECHARGE ACTIVE 37 1Gb: x4, x8, x16 DDR SDRAM t RP has been met. t RCD has been met. No data t WR ends, with t RP) begins. This device supports ...
Page 38
... H Notes: 1. CKE clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay ...
Page 39
... PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN HIGH Row Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 1Gb: x4, x8, x16 DDR SDRAM Commands ©2003 Micron Technology, Inc. All rights reserved. ...
Page 40
... PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 1Gb: x4, x8, x16 DDR SDRAM Commands ©2003 Micron Technology, Inc. All rights reserved. ...
Page 41
... Ai is the most significant column address bit for a given density ( HIGH Col EN AP DIS AP Bank Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 1Gb: x4, x8, x16 DDR SDRAM Commands ©2003 Micron Technology, Inc. All rights reserved. ...
Page 42
... All banks must be idle before an AUTO REFRESH command is issued. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). ...
Page 43
... DLL bit (set LMR command is issued, the same operating parameters should be utilized as in step 11. 20. Wait at least 21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with CKE HIGH are required between step 11 (DLL RESET) and any READ command. PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2 ...
Page 44
... Issue AUTO REFRESH command Assert NOP or DESELECT for t RFC time Optional LMR command to clear DLL bit Assert NOP or DESELECT for t MRD time DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. 44 1Gb: x4, x8, x16 DDR SDRAM Operations © ...
Page 45
... V , and V + 0.3V. Alternatively, V REF are 0V, provided a minimum of 42Ω of series resistance is used between DD DD supply and the input pin. Once initialized 1Gb: x4, x8, x16 DDR SDRAM Tc0 Td0 Te0 ( ( ( ( ( ( ) ) ) ) ...
Page 46
... REGISTER DEFINITION Mode Register The mode register is used to define the specific DDR SDRAM mode of operation. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 21. The mode register is programmed via the LMR command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or until the device loses power (except for bit A8, which is self- clearing) ...
Page 47
... Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 21 on page 46. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command locations are available for both the sequential and the interleaved burst types ...
Page 48
... PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ READ NOP READ NOP READ NOP Transitioning Data 48 1Gb: x4, x8, x16 DDR SDRAM T2 T2n T3 T3n NOP NOP T2 T2n T3 T3n NOP NOP T2 T3 T3n NOP NOP Don’t Care AC, DQSCK, and DQSQ. ...
Page 49
... Allowable Operating Clock Frequency (MHz 2.5 75 ≤ f ≤ 167 75 ≤ f ≤ 167 75 ≤ f ≤ 133 Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 1Gb: x4, x8, x16 DDR SDRAM Operations 133 ≤ f ≤ 200 – – ©2003 Micron Technology, Inc. All rights reserved. ...
Page 50
... RCD specification. t RCD specification of 20ns with a 133 MHz clock (7.5ns period ≤ 3 (Figure 24 also shows the same case for RCD (MIN)/ Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 1Gb: x4, x8, x16 DDR SDRAM Address bus Extended mode ...
Page 51
... CK and CK#). Figure 25 on page 53 shows the general timing for each possible CL setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble ...
Page 52
... RP have been met. Part of the row precharge time is hidden during the access of the last data elements. PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN 1Gb: x4, x8, x16 DDR SDRAM t DQSS (NOM) case is shown; the t DQSS [MIN] and Micron Technology, Inc ...
Page 53
... T1 T2 READ NOP NOP Bank a, Col 2 READ NOP NOP Bank a, Col AC, DQSCK, and Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 1Gb: x4, x8, x16 DDR SDRAM T2n T3 T3n T4 NOP NOP n T2n T3 T3n T4 NOP NOP T3n T4 T4n NOP NOP DO ...
Page 54
... Bank, Bank, Col n Col 2 READ NOP READ Bank, Bank, Col n Col AC, DQSCK, and Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 1Gb: x4, x8, x16 DDR SDRAM T2n T3 T3n T4 T4n NOP NOP DO b T2n T3 T3n T4 T4n NOP NOP T3n ...
Page 55
... NOP NOP READ Bank, Col AC, DQSCK, and DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 T5n NOP NOP DO b T3n T4 T5 T5n NOP NOP DO b T3n T4 T4n T5 NOP ...
Page 56
... Col n Col x Col READ READ READ Bank, Bank, Bank, Col n Col x Col 2 READ READ READ Bank, Bank, Bank, Col n Col x Col AC, DQSCK, and 56 1Gb: x4, x8, x16 DDR SDRAM T3 T3n T4 T4n T5 READ NOP Bank, Col T2n T3 T3n T4 T4n READ NOP Bank, Col ...
Page 57
... BST 1 READ NOP Bank a, Col 2 BST 1 READ NOP Bank a, Col AC, DQSCK, and 57 1Gb: x4, x8, x16 DDR SDRAM T2n T3 T4 NOP NOP T2n T3 T4 NOP NOP T3n T4 NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 58
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ NOP BST NOP BST BST NOP AC, DQSCK, and 58 1Gb: x4, x8, x16 DDR SDRAM T2n T3 T4 T4n WRITE NOP Bank, Col b t DQSS (NOM T2n T3 T3n T4 NOP WRITE Bank, Col b t DQSS (NOM T3n ...
Page 59
... RAS (MIN) is met, a READ command with auto precharge enabled would cause AC, DQSCK, and DQSQ. t RAS (MIN) is met. Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 1Gb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n T4 NOP NOP t RP T2n T3 T3n ...
Page 60
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ NOP READ NOP t IH Col Bank RCD t RAS (MIN) 60 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n PRE NOP NOP All banks One bank 5 Bank RPRE DQSCK (MIN) RPST (MIN) AC (MIN RPRE DQSCK (MAX) RPST DO ...
Page 61
... DQS DQ (last data valid (last data valid) 6 Earliest signal transition Latest signal transition clock transition collectively when a bank is active HP QHS. 61 1Gb: x4, x8, x16 DDR SDRAM T2 T2n T3 T3n DQSQ 2 t DQSQ T2n T3 T2 T2n T3 T2 T2n T3 Data Data Data valid valid valid ...
Page 62
... Data valid window clock transition collectively when a bank is active HP QHS. 62 1Gb: x4, x8, x16 DDR SDRAM T2n T3 T3n DQSQ 2 t DQSQ 2 t DQSQ T2n T3 T2n T3 T2n T3 Data valid Data valid Data valid window window t DQSQ 2 t DQSQ 2 t DQSQ T2n T3 T2n T3 T2n ...
Page 63
... AC (MIN) are the first valid signal transitions (MAX) are the latest valid signal transitions DQSS [MIN] and Micron Technology, Inc., reserves the right to change products or specifications without notice. 63 1Gb: x4, x8, x16 DDR SDRAM T3 T3n T4 T4n T5 t DQSCK 2 (MAX) t DQSCK 2 (MIN) T3 ...
Page 64
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ WTR should be met, as shown in Figure period are written to the internal array; any subsequent data-in Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 1Gb: x4, x8, x16 DDR SDRAM Operations t WTR period are written t WR should be met, as shown met. © ...
Page 65
... Bank a, Col b t DQSS DQS DQSS DQS DQSS DQS Transitioning Data 65 1Gb: x4, x8, x16 DDR SDRAM T2 T2n T3 NOP NOP Don’t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Operations ...
Page 66
... WRITE NOP WRITE Bank, Bank, Col b Col n t DQSS DI b Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 1Gb: x4, x8, x16 DDR SDRAM Operations T2n T3 T3n T4 T4n NOP NOP DI n Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. ...
Page 67
... T1n CK WRITE NOP Bank, Col b t DQSS T1n WRITE WRITE Bank, Bank, Col b Col x t DQSS (NOM 1Gb: x4, x8, x16 DDR SDRAM T2 T2n T3 T4 NOP WRITE NOP Bank, Col Transitioning Data T2 T2n T3 T3n T4 WRITE WRITE WRITE Bank, Bank, Bank, Col n Col a ...
Page 68
... T2n T3 NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 1Gb: x4, x8, x16 DDR SDRAM T4 T5 READ NOP WTR Bank a, Col Transitioning Data t WTR is not required, and the READ ©2003 Micron Technology, Inc. All rights reserved. ...
Page 69
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col Micron Technology, Inc., reserves the right to change products or specifications without notice. 69 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 T5n NOP NOP Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. T6 T6n NOP Don’ ...
Page 70
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ T1n T2 T2n T3 NOP NOP READ t WTR Bank a, Col Micron Technology, Inc., reserves the right to change products or specifications without notice. 70 1Gb: x4, x8, x16 DDR SDRAM Operations T3n T4 T5 T5n NOP NOP Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. T6 ...
Page 71
... DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/ T1n T2 T2n T3 NOP NOP NOP 1Gb: x4, x8, x16 DDR SDRAM T4 T5 PRE NOP Bank all) Transitioning Data not required, and Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’ ...
Page 72
... T1 T1n T2 T2n T3 NOP NOP NOP 1Gb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 NOP PRE t RP Bank all) Transitioning Data Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’t Care ...
Page 73
... T1 T1n T2 T2n T3 NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. 73 1Gb: x4, x8, x16 DDR SDRAM T3n T4 T4n T5 PRE NOP t RP Bank all) Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. Operations T6 NOP Don’t Care ...
Page 74
... Bank x t RCD t RAS t DQSS (NOM WPRES WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 74 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T7 NOP 1 NOP 1 NOP DQSL DQSH WPST Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. ...
Page 75
... WRITE NOP Col Bank x t RCD t RAS t DQSS (NOM) t WPRES t WPRE Micron Technology, Inc., reserves the right to change products or specifications without notice. 75 1Gb: x4, x8, x16 DDR SDRAM T4n T5 T5n NOP NOP NOP DQSL t DQSH t WPST Transitioning Data ©2003 Micron Technology, Inc. All rights reserved. ...
Page 76
... DQSH Transitioning Data t DQSS (MIN). t DQSS (MAX). Micron Technology, Inc., reserves the right to change products or specifications without notice. 76 1Gb: x4, x8, x16 DDR SDRAM Operations T2n T3 t DSS 3 t WPST Don’t Care t RP) after the t RAS (MIN), as described for t RP) is completed. ...
Page 77
... READ NOP Col Bank x t RCD, t RAP RAS RPRE t LZ (MIN (MIN) t RAS has been satisfied. Micron Technology, Inc., reserves the right to change products or specifications without notice. 77 1Gb: x4, x8, x16 DDR SDRAM T5 T5n T6 T6n NOP NOP NOP DQSCK (MIN) t RPST (MIN) ...
Page 78
... AUTO REFRESH command and the next AUTO REFRESH command is 9 × specifications exceed the JEDEC requirement by one clock. This maximum absolute interval is to allow future support for DLL updates, internal to the DDR SDRAM restricted to AUTO REFRESH cycles, without allowing excessive drift in updates. ...
Page 79
... DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown. SELF REFRESH When in the self refresh mode, the DDR SDRAM retains data without external clocking. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “ ...
Page 80
... XSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command can be applied general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the ...
Page 81
... Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined when the read postamble is satisfied; for WRITEs, when the write recovery time ...
Page 82
... Valid DQS DQ DM Enter 3 power-down mode must always be powered within the specified range. REF ® their respective owners. characterization sometimes occur. Micron Technology, Inc., reserves the right to change products or specifications without notice. 82 1Gb: x4, x8, x16 DDR SDRAM T2 Ta0 Ta1 ( ( ) ) ( ( ) ) ...