MT46V128M8P-6T:A Micron Technology Inc, MT46V128M8P-6T:A Datasheet - Page 9

• Manufacturer Part Number: MT46V128M8P-6T:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 128Mx8 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V128M8P-6T:A

• Density: 1 Gb
• Maximum Clock Rate: 333 MHz
• Package: 66TSOP
• Address Bus Width: 16 Bit
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 128Mx8
• Address Bus: 16b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 230mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
1Gb_DDR_x4x8x16_D2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
3, 9, 15, 55, 61
29, 30, 31, 32,
35, 36, 37, 38,
54, 56, 57, 59,
60, 62, 63, 65
56, 59, 62, 65
8, 10, 11, 13,
5, 11, 56, 62
39, 40, 28,
2, 5, 8, 11,
Numbers
41, 42, 17
2, 4, 5, 7,
1, 18, 33
23, 22,
26, 27
45, 46
20, 47
TSOP
44
24
47
21
51
16
51
Pin Descriptions
A0, A1, A2, A3,
A4, A5, A6, A7,
A11, A12, A13
A8, A9, A10,
DQ12–DQ15
RAS#, CAS#,
DQ8–DQ11
LDM, UDM
DQ0–DQ3
DQ4–DQ7
DQ0–DQ3
DQ4–DQ7
DQ0–DQ3
BA0, BA1
Symbol
CK, CK#
UDQS
V
LDQS
WE#
DQS
CKE
V
CS#
DM
DD
DD
Q
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER (LMR) command.
Bank address inputs: BA0 and BA1 define the bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 also
define which mode register (mode register or extended mode register) is
loaded during the LOAD MODE REGISTER command.
Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
the negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers, and output drivers. Taking CKE LOW provides
PRECHARGE power-down and SELF REFRESH operations (all banks idle) or
ACTIVE power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous
for self refresh exit and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers (excluding CK, CK#,
and CKE) are disabled during power-down. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS
HIGH, after which it becomes a SSTL_2 input only.
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
write access. DM is sampled on both edges of DQS. Although DM pins are
input-only, the DM loading is designed to match that of DQ and DQS pins.
For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15. Pin 20
is a NC on x4 and x8.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Data input/output: Data bus for x16.
Data input/output: Data bus for x8.
Data input/output: Data bus for x4.
Data strobe: Output with read data, input with write data. DQS is edge-
aligned with read data, center-aligned with write data. It is used to capture
data. For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is DQS for DQ8–
DQ15. Pin 16 is NC on x4 and x8.
Power supply.
DQ power supply: Isolated on the die for improved noise immunity.
LOW level after V
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Pin Assignments and Descriptions
is applied and until CKE is first brought
1Gb: x4, x8, x16 DDR SDRAM
©2003 Micron Technology, Inc. All rights reserved.