XC95108-15PC84I Xilinx Inc, XC95108-15PC84I Datasheet - Page 10

CPLD XC9500 Family 2.4K Gates 108 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 84-Pin PLCC

XC95108-15PC84I

Manufacturer Part Number
XC95108-15PC84I
Description
CPLD XC9500 Family 2.4K Gates 108 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 84-Pin PLCC
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets

Specifications of XC95108-15PC84I

Package
84PLCC
Family Name
XC9500
Device System Gates
2400
Number Of Macro Cells
108
Maximum Propagation Delay Time
15 ns
Number Of User I/os
69
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
55.6 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
6
Number Of Macrocells
108
Number Of Gates
2400
Number Of I /o
69
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
5V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1246
XC95108-15PC84I

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XC9500 In-System Programmable CPLD Family
Fast CONNECT Switch Matrix
The Fast CONNECT switch matrix connects signals to the
FB inputs, as shown in
sponding to user pin inputs) and all FB outputs drive the
Fast CONNECT matrix. Any of these (up to a FB fan-in limit
of 36) may be selected, through user programming, to drive
each FB with a uniform delay.
10
Wired-AND
Capability
Figure
Fast CONNECT
Switch Matrix
9. All IOB outputs (corre-
(36)
(36)
Figure 9: Fast CONNECT Switch Matrix
www.xilinx.com
Function Block
Function Block
The Fast CONNECT switch matrix is capable of combining
multiple internal connections into a single wired-AND output
before driving the destination FB. This provides additional
logic capability and increases the effective logic fan-in of the
destination FB without any additional timing delay. This
capability is available for internal connections originating
from FB outputs only. It is automatically invoked by the
development software where applicable.
D/T Q
D/T Q
18
18
DS063 (v5.5) June 25, 2007
I/O Block
I/O Block
Product Specification
DS063_09_110501
I/O
I/O
R

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