XC95108-15PC84I Xilinx Inc, XC95108-15PC84I Datasheet - Page 15

• Manufacturer Part Number: XC95108-15PC84I
• Description: CPLD XC9500 Family 2.4K Gates 108 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-15PC84I

• Package: 84PLCC
• Family Name: XC9500
• Device System Gates: 2400
• Number Of Macro Cells: 108
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 69
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1246; XC95108-15PC84I

DS063 (v5.5) June 25, 2007
Product Specification
T
PSU
R
All resources within FB using local Feedback
Setup Time = T
T
T
T
Propagation Delay = T
T
GCK
GSR
GTS
Internal Cycle Time = T
IN
Combinatorial
P-Term Clock
Combinatorial
Combinatorial
Logic
Logic
Path
Logic
(a)
PSU
(e)
(c)
T
Pin Feedback
T
T
T
T
LOGILP
PD
Clock to Out Time = T
PTCK
PTSR
PTTS
LOGI
CNT
D/T Q
D/T Q
Figure 15: Detailed Timing Model
Figure 14: Basic Timing Model
S*T
www.xilinx.com
T
PTA
PCO
PCO
D/T
EC
T
T
SUI
HI
T
T
T
SR
T
PDI
AOI
RAI
F
T
Macrocell
COI
XC9500 In-System Programmable CPLD Family
Setup Time = T
Q
Internal System Cycle Time = T
Combinatorial
Combinatorial
Logic
Logic
SU
T
(b)
OUT
(d)
Clock to Out Time = T
D/T Q
D/T Q
T
SLEW
SYSTEM
DS063_14_110501
DS063_15_110501
T
CO
T
EN
CO
15