XC95108-15PC84I Xilinx Inc, XC95108-15PC84I Datasheet - Page 11

• Manufacturer Part Number: XC95108-15PC84I
• Description: CPLD XC9500 Family 2.4K Gates 108 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-15PC84I

• Package: 84PLCC
• Family Name: XC9500
• Device System Gates: 2400
• Number Of Macro Cells: 108
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 69
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1246; XC95108-15PC84I

I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins. Each IOB includes an input
buffer, output driver, output enable selection multiplexer,
and user programmable ground control. See
details.
The input buffer is compatible with standard 5V CMOS, 5V
TTL, and 3.3V signal levels. The input buffer uses the internal
DS063 (v5.5) June 25, 2007
Product Specification
Macrocell
(Inversion in
I/O/GTS1
AND-array)
I/O/GTS2
I/O/GTS3
I/O/GTS4
R
Product Term OE
To Fast CONNECT
Switch Matrix
Figure 10: I/O Block and Output Enable Capability
Global OE 1
Global OE 2
Global OE 3
Global OE 4
PTOE
OUT
Figure 10
www.xilinx.com
for
5V voltage supply (V
olds are constant and do not vary with the V
The output enable may be generated from one of four
options: a product term signal from the macrocell, any of the
global OE signals, always [1], or always [0]. There are two
global output enables for devices with up to 144 macrocells,
and four global output enables for the rest of the devices.
Both polarities of any of the global 3-state control (GTS)
pins may be used within the device..
Macrocells
To other
XC9500 In-System Programmable CPLD Family
1
0
Available in
XC95216
and XC95288
Slew Rate
Control
CCINT
Programmable
) to ensure that the input thresh-
Ground
User-
Resistor*
Pull-up
V
I/O Block
CCIO
DS063_10_092203
CCIO
I/O
voltage.
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