XC95108-15PC84I Xilinx Inc, XC95108-15PC84I Datasheet - Page 14

• Manufacturer Part Number: XC95108-15PC84I
• Description: CPLD XC9500 Family 2.4K Gates 108 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-15PC84I

• Package: 84PLCC
• Family Name: XC9500
• Device System Gates: 2400
• Number Of Macro Cells: 108
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 69
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1246; XC95108-15PC84I

XC9500 In-System Programmable CPLD Family
Low Power Mode
All XC9500 devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipa-
tion. Macrocells programmed for low-power mode incur
additional delay (T
well as register setup time. Product term clock to output and
product term output enable delays are unaffected by the
macrocell power-setting.
Timing Model
The uniformity of the XC9500 architecture allows a simpli-
fied timing model for the entire device. The basic timing
14
Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
LP
) in pin-to-pin combinatorial delay as
(a)
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model, shown in
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in
terms are available with a span of 1. In the case of
the 18 product term function has a span of 2.
Detailed timing information may be derived from the full tim-
ing model shown in
for each parameter are given in the individual device data
sheets.
Figure
Figure
Figure 6
(b)
14, is valid for macrocell functions
15. The values and explanations
shows that up to 15 product
DS063 (v5.5) June 25, 2007
Product Specification
X5902
Table 4
shows how
Figure
7,
R