IDT5T9306NLI IDT, Integrated Device Technology Inc, IDT5T9306NLI Datasheet - Page 3

• Manufacturer Part Number: IDT5T9306NLI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of IDT5T9306NLI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 1000MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Package Type: VFQFPN
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Quiescent Current: 240mA
• Lead Free Status / RoHS Status: Not Compliant

ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. Not to exceed 3.6V.
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
IDT
NOTES:
1. Inputs are capable of translating the following interface standards:
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
Symbol
Symbol
V
V
V
T
T
STG
J
GND
DD
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
A
A
IDT5T9306
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
I
O
SEL
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
pulses or be able to tolerate them in down stream circuitry.
up after asserting PD.
V
N C
GL
Qn
Q n
P D
™
Symbol
[1:2]
G
[1:2]
DD
/ ICS
V
T
DD
A
™
Power Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Junction Temperature
LVDS CLOCK BUFFER TERABUFFER™ II
I/O
O
O
I
I
I
I
I
I
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Adjustable
Adjustable
LVTTL
LVTTL
LVTTL
LVTTL
LVDS
LVDS
Description
Type
PWR
PWR
(2)
(1,4)
(1,4)
Description
Clock input. A
Complementary clock inputs. A
desired toggle voltage for A
Gate control for differential outputs Q
HIGH, the differential outputs are asynchronously driven to the level designated by GL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputs disable LOW and "complementary" outputs disable HIGH.
Clock outputs
Complementary clock outputs
Reference clock select. When LOW, selects A
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to V
Power supply for the device core and inputs
Power supply return for all power
No connect; recommended to connect to GND
[1:2]
–0.5 to V
is the "true" side of the differential clock input.
–0.5 to +3.6
–0.5 to +3.6
–65 to +150
Max
150
DD
[1:2]
+0.5
3.3V LVTTL V
2.5V LVTTL V
(1)
:
[1:2]
is the complementary side of A
1
Unit
and Q
° C
° C
V
V
V
REF
REF
1
through Q
3
2
= 1650mV
= 1250mV
CAPACITANCE
NOTE:
1. This parameter is measured at characterization but not tested
DD
and A
Symbol
C
. Set HIGH for normal operation.
IN
2
6
. When HIGH, selects A
and Q
Min.
–40
2.3
Input Capacitance
6
. When G is LOW, the differential outputs are active. When G is
Parameter
[1:2].
For LVTTL single-ended operation, A
Typ.
+25
(1)
2.5
1
and A
(3)
(2)
(T
.
A
1
.
IDT5T9306 REV. B October 21, 2008
= +25°C, F = 1.0MHz)
Min
—
Max.
+85
2.7
Typ.
—
[1:2]
Max.
should be set to the
3
Unit
° C
V
Unit
pF