IDT5T93GL161PFI IDT, Integrated Device Technology Inc, IDT5T93GL161PFI Datasheet

IDT5T93GL161PFI

Manufacturer Part Number
IDT5T93GL161PFI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of IDT5T93GL161PFI

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
450MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
TQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Quiescent Current
350mA
Lead Free Status / RoHS Status
Not Compliant
2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
General Description
The IDT5T93GL161 2.5V differential clock buffer is a
user-selectable differential input to sixteen LVDS outputs. The
fanout from a differential input to sixteen LVDS outputs reduces
loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL161 can act as a translator
from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V
/ 2.5V LVTTL input can also be used to translate to LVDS outputs.
The redundant input capability allows for
from a primary clock source to a secondary clock source.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable LOW for up to three clock cycles of the
previously-selected input clock. The outputs will remain LOW for
up to three clock cycles of the newly-selected clock, after which
the outputs will start from the newly-selected input. A FSEL pin
has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL161 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the
value selected by the GL pin. Multiple power and grounds reduce
noise.
Applications
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
Clock distribution
a
glitchless change-over
1
GND
GND
GND
Pin Assignment
Features
V
V
G1
Q1
Q3
Q4
Q4
Q1
Q2
Q2
Q3
A1
A1
DD
DD
Guaranteed low skew: <75ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to sixteen LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
-40°C to 85°C ambient operating temperature
Available in TQFP package
1
2
3
4
5
6
8
10
11
12
13
14
15
16
7
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DD
10mm x 10mm x 1.0mm package body
64-Lead TQFP E-Pad
IDT5T93GL161
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Y package
Top View
IDT5T93GL161
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
36
G2
GND
GND
V
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
V
A2
A2
GND
DD
DD

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IDT5T93GL161PFI Summary of contents

Page 1

LVDS, 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II General Description The IDT5T93GL161 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding ...

Page 2

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Block Diagram SEL FSEL G2 IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ OUTPUT CONTROL Q1 Q2 OUTPUT CONTROL Q2 Q3 OUTPUT ...

Page 3

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 1. Pin Descriptions Name Type A[1:2] Input Adjustable A[1:2] Input Adjustable G1 Input LVTTL G2 Input LVTTL GL Input LVTTL Q[1:16] Output LVDS Q{1:16} Output LVDS SEL Input LVTTL PD ...

Page 4

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Function Tables Table 3A. Gate Control Output Table Control Outputs GL G Q[1:16 Toggling 0 1 LOW 1 0 Toggling 1 1 HIGH Table 3B. Input Selection Table Selection ...

Page 5

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these ...

Page 6

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 4B. LVTTL DC Characteristics Symbol Parameter I Input High Current IH I Input Low Current IL V Clamp Diode Voltage Input Voltage Input High ...

Page 7

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 4D. LVDS DC Characteristics Symbol Parameter Differential Output Voltage for the V OT(+) True Binary State Differential Output Voltage for the V OT(–) False Binary State Change in V Between ...

Page 8

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5B. eHSTL AC Differential Input Characteristics, T Symbol Parameter (1) V Input Signal Swing DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement ...

Page 9

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Table 5E. AC Differential Input Characteristics Symbol Parameter ( Differential Voltage DIF V Differential Input Cross Point Voltage IX V Common Mode Input Voltage Range CM V Input Voltage ...

Page 10

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Differential AC Timing Waveforms Output Propagation and Skew Waveforms 1/ [1:2] [1:2] t PLH SK( NOTE 1: Pulse skew is calculated ...

Page 11

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Glitchless Output Operation with Switching Input Clock Selection SEL When SEL changes, the output clock goes LOW ...

Page 12

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II FSEL Operation for When Opposite Clock Dies 1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this ...

Page 13

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Power Down Timing NOTE recommended that outputs be disabled before entering power-down mode. ...

Page 14

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuits and Conditions Test Circuit for Differential Input Pulse Generator Table 6A. Differential Input Test Conditions Symbol V = 2.5V ± 0. Crossing of A and A THI ...

Page 15

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Test Circuit for DC Outputs and Power Down Tests V A Pulse Generator D.U.T. A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing A Pulse Generator D.U.T. A Table 6B. ...

Page 16

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Package Outline IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ IDT5T93GL161 REV. A SEPTEMBER 12, 2008 ...

Page 17

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Package Dimensions IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ IDT5T93GL161 REV. A SEPTEMBER 12, 2008 ...

Page 18

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Ordering Information Table 7. Ordering Information XX IDT XXXXX Package Device Type IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ Process I PF PFG 5T93GL161 2.5V LVDS 1:16 Glitchless Clock Buffer ...

Page 19

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Revision History Sheet Rev Table Page Description of Change T3A 4 Added Gate Control Output Table. T3B 4 Added Selection Table Added Package Outline. 17 Added Package Dimensions. Updated ...

Page 20

IDT5T93GL161 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and ...

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