ICS8530DY-01 IDT, Integrated Device Technology Inc, ICS8530DY-01 Datasheet

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ICS8530DY-01

Manufacturer Part Number
ICS8530DY-01
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of ICS8530DY-01

Lead Free Status / RoHS Status
Supplier Unconfirmed

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Quantity
Price
Part Number:
ICS8530DY-01LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS8530DY-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
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20 000
B
G
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
Guaranteed output and part-to-part skew characteristics make
the ICS8530-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
8530DY-01
HiPerClockS™
IC S
LOCK
ENERAL
nCLK
CLK
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D
The ICS8530-01 is a low skew, 1-to-16 Differen-
tial-to-3.3V LVPECL Fanout Buffer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
www.icst.com/products/hiperclocks.html
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
D
IFFERENTIAL
1
P
F
• Sixteen differential 3.3V LVPECL outputs
• CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to
• Output skew: 75ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
3.3V LVPECL levels with a resistor bias on nCLK input
packages
IN
EATURES
nQ11
nQ10
A
V
V
Q11
Q10
nQ9
nQ8
V
CCO
V
CCO
Q9
Q8
CC
EE
SSIGNMENT
-
TO
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
9
10
11
12
-3.3V LVPECL F
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
ICS8530-01
48-Pin LQFP
Y Package
Top View
L
OW
ICS8530-01
S
ANOUT
KEW
36
35
34
33
32
31
30
29
28
27
26
25
REV. E MAY 19, 2006
, 1-
CLK
V
nQ0
Q0
nQ1
Q1
V
nQ2
Q2
nQ3
Q3
Vcco
B
CCO
EE
TO
UFFER
-16

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ICS8530DY-01 Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8530- low skew, 1-to-16 Differen tial-to-3.3V LVPECL Fanout Buffer and a mem- HiPerClockS™ ber of the HiPerClockS™ family of High Perfor- mance Clock Solutions from ICS. The ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE ...

Page 4

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc. The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise ...

Page 6

Integrated Circuit Systems, Inc. P ARAMETER CCO LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW nCLK CLK nQ0:nQ15 ...

Page 7

Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ generated by the bias resistors ...

Page 8

Integrated Circuit Systems, Inc IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show inter- PP ...

Page 9

Integrated Circuit Systems, Inc. T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termi- nation for LVPECL outputs. The two different layouts men- tioned are recommended only as guidelines. FOUT and nFOUT are low ...

Page 10

Integrated Circuit Systems, Inc. This section provides information on power dissipation and junction temperature for the ICS8530-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8530-01 is the sum of the core ...

Page 11

Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case ...

Page 12

Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data ...

Page 13

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR ABLE ...

Page 14

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

Page 15

Integrated Circuit Systems, Inc " ...

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