ICS8530DY-01 IDT, Integrated Device Technology Inc, ICS8530DY-01 Datasheet - Page 7

• Manufacturer Part Number: ICS8530DY-01
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS8530DY-01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

W
V
8530DY-01
Figure 1 shows how the differential input can be wired to
accept single ended levels. The reference voltage V_REF ~
bias circuit should be located as close as possible to the
R
O
LVPECL O
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
CC
ECOMMENDATIONS FOR
UTPUTS
IRING THE
/2 is generated by the bias resistors R1, R2 and C1. This
:
UTPUT
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
U
F
NUSED
I
IGURE
NPUT TO
Single Ended Clock Input
1. S
O
A
UTPUT
A
INGLE
www.icst.com/products/hiperclocks.html
PPLICATION
CCEPT
P
E
C1
0.1u
INS
NDED
S
V_REF
INGLE
D
S
IGNAL
IFFERENTIAL
E
7
NDED
I
input pin. The ratio of R1 and R2 might need to be adjusted to
position the V_REF in the center of the input voltage swing.
For example, if the input clock swing is only 2.5V and V
3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
D
NFORMATION
1K
R1
1K
R2
RIVING
VCC
L
EVELS
CLK
nCLK
D
-
IFFERENTIAL
TO
-3.3V LVPECL F
I
NPUT
L
OW
ICS8530-01
S
ANOUT
KEW
REV. E MAY 19, 2006
, 1-
B
TO
UFFER
-16
CC
=