IDT82V3012PV IDT, Integrated Device Technology Inc, IDT82V3012PV Datasheet - Page 26

• Manufacturer Part Number: IDT82V3012PV
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLLr

Specifications of IDT82V3012PV

• Number Of Elements: 1
• Supply Current: 60mA
• Pll Input Freq (min): 8KHz
• Pll Input Freq (max): 19.44MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Output Frequency Range: Up to 155.52MHz
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Not Compliant

Notes:
operating temperature are as per Recommended Operating Conditions. Timing
parameters are as per Timing Parameter Measurement Voltage Levels.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Master clock input OSCi at 20 MHz ±0 ppm.
11. Master clock input OSCi at 20 MHz ±32 ppm.
12. Master clock input OSCi at 20 MHz ±100 ppm.
13. Selected reference input at ±0 ppm.
14. Selected reference input at ±32 ppm.
15. Selected reference input at ±100 ppm.
16. For Freerun mode of ±0 ppm.
17. For Freerun mode of ±32 ppm.
18. For Freerun mode of ±100 ppm.
19. For capture range of ±230 ppm.
20. For capture range of ±198 ppm.
21. For capture range of ±130 ppm.
AC Electrical Characteristics
IDT82V3012
Voltages are with respect to ground (V
Fref0 reference input selected.
Fref1 reference input selected.
Normal mode selected.
Holdover mode selected.
Freerun mode selected.
8 kHz frequency mode selected.
1.544 MHz frequency mode selected.
2.048 MHz frequency mode selected.
19.44 MHz frequency mode selected.
SS
) unless otherwise stated. Supply voltage and
26
22. 25 pF capacitive load.
23. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
24. Jitter on reference input is less than 7 nspp.
25. Applied jitter is sinusoidal.
26. Minimum applied input jitter magnitude to regain synchronization.
27. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
28. Within 10 ms of the state, reference or input change.
29. 1 UIpp = 125 µs for 8 kHz signals.
30. 1 UIpp = 648 ns for 1.544 MHz signals.
31. 1 UIpp = 488 ns for 2.048 MHz signals.
32. 1 UIpp = 323 ns for 3.088 MHz signals.
33. 1 UIpp = 244 ns for 4.096 MHz signals.
34. 1 UIpp = 158 ns for 6.312 MHz signals.
35. 1 UIpp = 122 ns for 8.192 MHz signals.
36. 1 UIpp = 61 ns for 16.484 MHz signals.
37. 1 UIpp = 51 ns for 19.44 MHz signals.
38. 1 UIpp = 30 ns for 32.968 MHz signals.
39. No filter.
40. 40 Hz to 100 kHz bandpass filter.
41. With respect to reference input signal frequency.
42. After a RST or TCLR .
43. Master clock duty 40% to 60%.
44. Prior to Holdover mode, device as in Normal mode and phase locked.
45. With input frequency offset of 100 ppm.
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
February 6, 2009