PCA2125TS/1-T NXP Semiconductors, PCA2125TS/1-T Datasheet - Page 24

• Manufacturer Part Number: PCA2125TS/1-T
• Description: Real Time Clock AUTO RL TME CLCK/CAL
• Manufacturer: NXP Semiconductors

Specifications of PCA2125TS/1-T

• Bus Type: Serial (3-Wire, SPI)
• Package Type: TSSOP
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Date Format: DW:DM:M:Y
• Time Format: HH:MM:SS
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Lead Free Status / RoHS Status: Compliant
• Other names: PCA2125TS/1,118

NXP Semiconductors
PCA2125_1
Product data sheet
8.11 3-line SPI
Data transfer to and from the device is made via a 3-wire SPI-bus; see
lines for input and output are split. The data input and output lines can be connected
together to facilitate a bidirectional data bus. The chip enable signal is used to identify the
transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent
first; see
Table 37.
The transmission is controlled by the active HIGH chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Data is captured on the rising edge of the clock and transferred internally
on the falling edge.
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
Table 38.
In
10 minutes.
Pin
CE
SCL
SDI
SDO
Bit
7
6 to 4
3 to 0
Fig 18. Data transfer overview
Figure 19
Function
chip enable input
serial clock input
serial data input
serial data output
Figure
Symbol
R/W
SA
RA
Serial interface
Command byte definition
chip enable
the Seconds register is set to 45 seconds and the Minutes register to
data bus
18.
Value
0
1
001
00h to 0Fh register address range
Rev. 01 — 28 July 2008
COMMAND
Description
when LOW, the interface is reset; pull-down resistor included; active
input can be higher than V
permanently
when pin CE = LOW, this input might float; input can be higher than
V
when pin CE = LOW, this input might float; input can be higher than
V
push-pull output; drives from V
the falling edge of SCL
DD
DD
; input data is sampled on the rising edge of SCL
Description
data read or data write selection
write data
read data
subaddress; other codes will cause the device to ignore data
transfer
DATA
DATA
DD
, but must not be wired HIGH
SS
to V
SPI Real-time clock/calendar
DD
; output data is changed on
DATA
PCA2125
Table
© NXP B.V. 2008. All rights reserved.
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37. The data
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