77V106L25TFG IDT, Integrated Device Technology Inc, 77V106L25TFG Datasheet - Page 14

• Manufacturer Part Number: 77V106L25TFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V106L25TFG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Counters
software drivers) in evaluating communications conditions. It is anticipated that
these counters will be polled from time to time (user selectable) to evaluate
performance.
cells
cell count (without roll over) if the counter is read once/second. The
Symbol Error counter and HEC Error counter were given sufficient size to
indicate exact counts for low error-rate conditions. If these counters
overflow, a gross condition is occurring, where additional counter
resolution does not provide additional diagnostic benefit.
Reading Counters
Register to the bit location corresponding to the desired counter. This loads
counter’s value, and resets this counter to zero.
Counter Select Registers.
IDT77V106L25
Several condition counters are provided to assist external systems (e.g.
•
— 8 bits
— counts all invalid 5-bit symbols received
•
— 16 bits
— counts all transmitted cells
•
— 16 bits
— counts all received cells, excluding idle cells and HEC errored
•
— 5 bits
— counts all HEC errors received
The TxCell and RxCell counters are sized (16 bits) to provide a full
1. Decide which counter value is desired. Write to the Counter Select
Symbol Error Counters
Transmit Cell Counters
Receive Cell Counters
Receive HEC Error Counters
the High and Low Byte Counter Registers with the selected
Note:Only one counter may be enabled at any time in each of the
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value.
the Counter Select Registers.
counters after a specific counter has been selected in the Counter Selector
be calculated as follows:
LOOP TIMING FEATURE
applications where data needs to be repeated / transmitted using the
recovered clock. If the loop timing mode is enabled in the Enhanced
Control Register 1 bit 6, the recovered receive clock is used as to clock out
data on transmit side. In normal mode, the transmitter transmits data using
the multiplied oscillator clock.
Jitter in Loop Timing Mode
amount of jitter that gets added each time data is transmitted. Table 2 shows
the jitter measured at various data rates. The set-up shown in Figure 15
was used to perform these tests. The maximum jitter seen was at TX point
5 and the minimum jitter was at point 2. The loop timing jitter is defined as
the amount of jitter generated by each TX node. In other words, the loop
timing jitter or the jitter added by a loop-timed port in the set-up below is
the difference between the Total Output Jitter and the Total Input Jitter.
2. Read the Counter Registers (low byte and high byte) to get the
Further reads may be accomplished in the same manner by writing to
The 77V106L25 also offers a loop timing feature for specific
One of the primary concerns when using loop timing mode is the
Note:The PHY takes some time to set up the low and high byte
register. This time delay (in µS) varies with the line rate and can
Time delay (µS) =
line rate (Mbps)
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