77V106L25TFG IDT, Integrated Device Technology Inc, 77V106L25TFG Datasheet - Page 5

• Manufacturer Part Number: 77V106L25TFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V106L25TFG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

FUNCTIONAL DESCRIPTION
Transmission Convergence (TC) Sub Layer
Introduction
synchronization. Under control of a switch interface or Segmentation and
Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-byte ATM cell,
scrambles the data, appends a command byte to the beginning of the cell, and
encodes the entire 53 bytes before transmission. These data transformations
ensure that the signal is evenly distributed across the frequency spectrum. In
addition, the serialized bit stream is NRZI coded. An 8kHz timing sync pulse
may be used for isochronous communications.
Data Structure and Framing
distinguished by an escape symbol followed by one of 17 encoded symbols.
Together, this byte forms one of seventeen possible command bytes. Three
command bytes are defined:
cell command byte which resets both the transmitter-scrambler and receiver-
descrambler pseudo-random nibble generators (PRNG) to their initial states.
The following cell illustrates the insertion of a start-of-cell command without
scrambler/descrambler reset. During this cell’s transmission, an 8kHz timing
sync pulse triggers insertion of the X_8 8kHz timing marker command byte.
Transmission Description
An ATM layer device transfers a cell into the 77V106L25 across the Utopia
transmit bus. This cell enters a 3-cell deep transmit FIFO. Once a complete cell
is in the FIFO, transmission begins by passing the cell, four bits (MSB first) at
a time to the ‘Scrambler’.
the 4 high order bits (X(t), X(t-1), X(t-3)) of a 10 bit pseudo-random nibble
generator (PRING). Its function is to provide the appropriate frequency
distribution for the signal across the line.
IDT77V106L25
The TC sub layer defines the line coding, scrambling, data framing and
Each 53-byte ATM cell is preceded with a command byte. This byte is
1.
2.
3.
Below is an illustration of the cell structure and command byte usage:
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell}...
In the above example, the first ATM cell is preceded by the X_X start-of-
Refer to Figure 2. Cell transmission begins with the PHY-ATM Interface.
The ‘Scrambler’ takes each nibble of data and exclusive-ORs them against
X_X (read: ‘escape’ symbol followed by another ‘escape’): Start-of-
cell with scrambler/descrambler reset.
descrambler reset.
byte is generated when the 8kHz sync pulse is detected, and has
priority over all line activity (data or command bytes). It is transmitted
immediately when the sync pulse is detected. When this occurs
during a cell transmission, the data transfer is temporarily interrupted
on an octet boundary, and the X_8 command byte is inserted. This
condition is the only allowed interrupt in an otherwise contiguous
transfer.
X_4 (‘escape’ followed by ‘4’): Start-of-cell without scrambler/
X_8 (‘escape’ followed by ‘8’): 8kHz timing marker. This command
5
whether the processed nibble is part of a data or command byte. Note however
that only data nibbles are scrambled. The entire command byte (X _C) is NOT
scrambled
illustration).
The PRNG is based upon the following polynomial:
generated from the following equations:
an X_X command is sent. An X_X command is initiated only at the beginning
of a cell transfer after the PRNG has cycled through all of its states (2
states). The first valid ATM data cell transmitted after power on will also be
accompanied with an X_X command byte. Each time an X_X command byte
is sent, the first nibble after the last escape (X) nibble is XOR’d with 1111b
(PRNG = 3FFx).
possibility of a reset PRNG start-of-cell command and a timing marker command
occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection
of the last two consecutive escape (X) nibbles will cause the PRNG to reset to
its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble
of the second consecutive escape pair.
are further encoded using a 4b/5b process. The 4b/5b scheme ensures that
an appropriate number of signal transitions occur on the line. A total of
seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles
and the one escape (X) nibble. The table below lists the 4-bit data with their
corresponding 5-bit symbols:
The PRNG is clocked every time a nibble is processed, regardless of
X
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1).
A scrambler lock between the transmitter and receiver occurs each time
Because a timing marker command (X_8) may occur at any time, the
Once the data nibbles have been scrambled using the PRNG, the nibbles
10
+ X
7
ESC(X) = 00010
+ 1
Data
0010
0110
1010
1110
0000
0100
1000
1100
Data
before
Symbol
Symbol
01010
01110
11010
11110
10101
00111
10010
10111
it’s
encoded
Data
0001
0101
1001
1101
0011
0111
1011
1111
Data
(see
Symbol
Symbol
01001
01101
11001
11101
01011
01111
11011
11111
3505 drw 05a
diagram
10
- 1 = 1023
for