IDT77V107L25PFI IDT, Integrated Device Technology Inc, IDT77V107L25PFI Datasheet - Page 16

• Manufacturer Part Number: IDT77V107L25PFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Interrupt Status Register
Address:0x01
Diagnostic Control Register
Address:0x02
IDT77V107
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1, 0
Bit
Bit
R
sticky
sticky
sticky
sticky
sticky
sticky
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Type
0
0 = Bad Signal
0
0
0
0
0
0
0 = normal
0
1
0 = normal
0 = normal
0 = normal
00 = normal
Initial State
Initial State
Reserved
Good Signal Bit See definitions earlier in this data sheet.
1 - Good Signal
0 - Bad Signal
HEC error cell received Set when a HEC error is detected on received cell.
"Short Cell" Received Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected
when receiving Start-of-Cell command bytes with fewer than 53 bytes between them.
Transmit Parity Error If Bit 4 of the Master Control Register (Transmit Data Parity Check) is set, this interrupt flags a
transmit data parity error condition. Odd parity is used.
Receive Signal Condition change This interrupt is set when the received 'signal' changes either from 'bad to good' or
from 'good to bad'.
Received Symbol Error Set when an undefined 5-bit symbol is received.
Receive FIFO Overflow Interrupt which indicates when the receive FIFO has filled and cannot accept additional data.
Force TxCLAV Deassert This feature can be used during line loopback mode to prevent cells from being passed
across the Utopia bus for transmission.
Reserved
Reserved
RFLUSH = Clear Receive FIFO This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC
signals this completion by clearing this bit.
Insert Transmit Payload Error Tells TC to insert cell payload errors in transmitted cells. This can be used to test error
detection and recovery systems at destination station, or, under loopback control, at the local receiving station. This pay-
load error is accomplished by flipping bit 0 of the last cell payload byte.
Insert Transmit HEC Error Tells TC to insert HEC error in Byte 5 of transmitted cells. This can be used to test error
detection and recovery systems in downstream switches, or, under loopback control, the local receiving station. The HEC
error is accomplished by flipping bit 0 of the HEC byte.
Loopback Control
bit # 1
0
1
1
0
0
0
1
Normal mode (receive from network)
PHY Loopback
Line Loopback
16 of 24
Function
Function
December 2004