IDT77V107L25PFI IDT, Integrated Device Technology Inc, IDT77V107L25PFI Datasheet - Page 18

• Manufacturer Part Number: IDT77V107L25PFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Interrupt Mask Register
Address:0x07
Enhanced Control Register
Address:0x08
Absolute Maximum Ratings
V
T
T
I
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliabilty.
Symbol
OUT
IDT77V107
7
6
5
4-0
Bit
BIAS
STG
TERM
7
6
5
4
3
2
1
0
Bit
W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
Note: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are
unmasked. These interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
Type
Terminal Voltage with
Respect to GND
Temperature Under Bias -55 to +125
Storage Temperature
DC Output Current
0 = not reset
0 = OSC
0
00000
Initial State
0
0
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
0 = interrupt enabled
Rating
Initial State
Software Reset 1 = Reset. This bit is self-clearing; it isn't necessary to write ""0"" to exit reset.
Transmit Line Clock (or Loop Timing Mode) When set to 0, the OSC input is used as the transmit line clock. When
set to 1, the recovered receive clock is used as the transmit line clock.
Reserved
Utopia Port Address These bits determine the 5-bit address of the Utopia port for both receive and transmit.
-0.5 to +5.5
-55 to +120
50
Value
Reserved
Reserved
HEC Error Cell.
Short Cell Error.
Transmit Parity Error.
Receive Signal Condition Change.
Received Cell Symbol Error.
Receive FIFO Overflow.
V
mA
Unit
C
C
Recommended DC Operating Conditions
VDD
GND
VIH
VIL
AVDD
AGND
VDIF
Symbol
18 of 24
Digital Supply Voltage
Digital Ground Voltage
Input High Voltage
Input Low Voltage
Analog Supply Voltage
Analog Ground Voltage
VDD - AVDD
Function
Parameter
Function
3.0
0
2.0
-0.3
3.0
0
-0.5
Min
3.3
0
____
____
3.3
0
0
Typ
December 2004
3.6
0
5.25
0.8
3.6
0
0.5
Max
V
V
V
V
V
V
V
Unit