UJA1065TW/3V3-T NXP Semiconductors, UJA1065TW/3V3-T Datasheet - Page 22
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UJA1065TW/3V3-T
Manufacturer Part Number
UJA1065TW/3V3-T
Description
Network Controller & Processor ICs HI SPEED CAN SYSTEM
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1065TW3V3-T.pdf
(76 pages)
Specifications of UJA1065TW/3V3-T
Number Of Transceivers
1
Power Down Mode
Standby
Operating Supply Voltage (min)
5.5V
Supply Current
10mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Product
Controller Area Network (CAN)
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
HTSSOP EP
Lead Free Status / RoHS Status
Compliant
Other names
UJA1065TW/3V3,518
NXP Semiconductors
UJA1065_7
Product data sheet
6.7.4.1 TXDC dominant clamping
6.7.4.2 RXDC recessive clamping
6.7.3 Termination control
6.7.4 Bus, RXD and TXD failure detection
In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated
to 0.5 × V
is disabled due to an overload condition both pins become floating.
The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in
All failures are signalled separately in the CANFD bits in the System Diagnosis register.
Any change (detection and recovery) forces an interrupt to the microcontroller, if this
interrupt is enabled.
Table 3.
If the TXDC pin is clamped dominant for longer than t
disabled. After the TXDC pin becomes recessive the transmitter is reactivated
automatically when detecting bus activity or manually by setting and clearing the CTC bit.
If the RXDC pin is clamped recessive while the CAN-bus is dominant the CAN transmitter
is disabled. The transmitter is reactivated automatically when RXDC becomes dominant
or manually by setting and clearing the CTC bit.
Failure
HxHIGH
HxGND
LxHIGH
LxGND
HxL
Bus dom
TXDC dom
RXDC reces
RXDC dom
Fig 9.
CAN wake-up timing diagram.
V2
wake-up
CAN-bus, RXD and TXD failure detection
CANH
CANL
via R
i
. In Off-line mode CANH and CANL are terminated to GND via R
Rev. 07 — 25 February 2010
CANH short-circuit to V
pin RXDC is continuously clamped recessive
pin RXDC is continuously clamped dominant
Description
CANH short-circuit to GND
CANL short-circuit to V
CANL short-circuit to GND
CANH short-circuit to CANL
bus is continuously clamped dominant
pin TXDC is continuously clamped dominant
t
CAN(dom1)
High-speed CAN/LIN fail-safe system basis chip
CC
CC
, V
, V
BAT14
BAT14
t
CAN(reces)
TXDC(dom)
or V
or V
BAT42
BAT42
t
the CAN transmitter is
CAN(dom2)
UJA1065
© NXP B.V. 2010. All rights reserved.
001aad446
Table
i
22 of 76
. If V2
3.