UJA1065TW/3V3-T NXP Semiconductors, UJA1065TW/3V3-T Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
UJA1065TW/3V3-T
Manufacturer Part Number
UJA1065TW/3V3-T
Description
Network Controller & Processor ICs HI SPEED CAN SYSTEM
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1065TW3V3-T.pdf
(76 pages)
Specifications of UJA1065TW/3V3-T
Number Of Transceivers
1
Power Down Mode
Standby
Operating Supply Voltage (min)
5.5V
Supply Current
10mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Product
Controller Area Network (CAN)
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
HTSSOP EP
Lead Free Status / RoHS Status
Compliant
Other names
UJA1065TW/3V3,518
NXP Semiconductors
UJA1065_7
Product data sheet
2.4 Power management
2.5 Fail-safe features
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus and LIN-bus
External voltage regulators can easily be incorporated in the power supply system
(flexible and fail-safe)
42 V battery-related high-side switch for driving external loads such as relays and
wake-up switches
Intelligent maskable interrupt output
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,
guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety-critical hardware
Detection and detailed reporting of failures:
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp-home output signal for activating application hardware in case system enters
Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software-initiated system reset
On-chip oscillator failure and watchdog alerts
Battery and voltage regulator undervoltages
CAN and LIN-bus failures (short-circuits and open-circuit bus wires)
TXD and RXD clamping situations and short-circuits
Clamped or open reset line
SPI message errors
Overtemperature warning
ECU ground shift (two selectable thresholds)
Rev. 07 — 25 February 2010
High-speed CAN/LIN fail-safe system basis chip
UJA1065
© NXP B.V. 2010. All rights reserved.
3 of 76