DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 51

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

5.3
Datasheet
Test Logic Reset
Run -Test/Idle
Capture - DR
Shift - DR
Update - DR
Capture - IR
Shift - IR
Update - IR
Pause - IR
Pause - DR
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
Table 30. TAP State Description
State
TAP Controller
The TAP controller is a 16 state synchronous state machine controlled by the TMS input and
clocked by TCK (
instruction, receiving data, transmitting data or in an idle state.
the states represented in
In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the
instruction register is set to the ICODE instruction.
The TAP controller stays in this state as long as TMS is low. Used to perform tests.
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shifts the selected test data registers by one stage tword its serial output.
Data is latched into the parallel output of the BSR when selected.
Used to load the instruction register with a fixed instruction.
Shifts the instruction register by one stage.
Loads a new instruction into the instruction register.
Momentarily pauses shifting of data through the data/instruction registers.
Temporary states that can be used to terminate the scanning process.
Figure
Figure
16).The TAP controls whether the LXT386 is in reset mode, receiving an
16.
Description
QUAD T1/E1/J1 Transceiver — LXT386
Table 30
describes in detail each of
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