DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 70

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DJLXT386LE.B2 S E001

Manufacturer Part Number
DJLXT386LE.B2 S E001
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT386LE.B2 S E001

Lead Free Status / RoHS Status
Not Compliant
LXT386 — QUAD T1/E1/J1 Transceiver
70
Valid write signal pulse width
Inactive write to inactive INT delay time
Chip select to RDY delay time
Active ready Low time
Inactive ready to tri-state delay time
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C
3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
Table 47. Intel Mode Write Timing Characteristics (Sheet 2 of 2)
Figure 23. Non-Multiplexed Intel Mode Write Timing
L
D7-D0
A4-A0
= 100pF on D0-D7, all other outputs are loaded with 50pF.
RDY
ALE
WR
INT
CS
(pulled High)
Tristate
Parameter
3
2
3
tDRDY
tSCSW
Tdrdy
Tvrdy
Trdyz
Sym
Tvwr
Tint
tSAW
Min
60
ADDRESS
0
tVRDY
tVWR
Typ
1
Max
10
12
40
3
tHCSW
WRITE DATA
tSDW
tDRDY
tHDW
Unit
ns
ns
ns
ns
ns
tHAW
tINT
Test Conditions
Datasheet
Tristate
tRDYZ

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