82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet

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82V2048DA

Manufacturer Part Number
82V2048DA
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 82V2048DA

Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant

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Part Number:
82V2048DAG
Manufacturer:
IDT
Quantity:
1 858
FEATURES
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
 2010- Integrated Device Technology, Inc.
Fully integrated octal T1/E1 short haul line interface which
supports 100 Ω T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω
E1 coaxial applications
Selectable Single Rail mode or Dual Rail mode and AMI or
B8ZS/HDB3 encoder/decoder
Built-in transmit pre-equalization meets G.703 & T1.102
Selectable transmit/receive jitter attenuator meets ETSI CTR12/
13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications
SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification
Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
RRINGn
TRINGn
RTIPn
TTIPn
Monitor
G.772
Loopback
Analog
Generator
Clock
Detector
Peak
Driver
OCTAL T1/E1 SHORT HAUL
LINE INTERFACE UNIT
Line
Slicer
Figure-1 Block Diagram
Control Interface
Waveform
CLK&Data
Detector
Recovery
Transmit
All Ones
Shaper
(DPLL)
LOS
Loopback
Digital
1
Low impedance transmit drivers with high-Z
Selectable hardware and parallel/serial host interface
Local, Remote and Inband Loopback test functions
Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
JTAG boundary scan for board test
3.3 V supply with 5 V tolerant I/O
Low power consumption
Operating temperature range: -40
Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
Register
Attenuator
Attenuator
One of Eight Identical Channels
File
Jitter
Jitter
Loopback
Remote
JTAG TAP
HDB3/AMI
HDB3/AMI
Decoder
Encoder
B8ZS/
B8ZS/
Generator
Detector
Detector
IBLC
AIS
IBLC
°C
to +85
°C
VDDIO
VDDT
VDDD
VDDA
IDT82V2048
BPVIn/TDNn
RDn/RDPn
TDn/TDPn
CVn/RDNn
TCLKn
July 1, 2010
RCLKn
LOSn
DSC-6037/19

Related parts for 82V2048DA

82V2048DA Summary of contents

Page 1

FEATURES Fully integrated octal T1/E1 short haul line interface which supports 100 Ω T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω E1 coaxial applications Selectable Single Rail mode or Dual Rail mode and AMI or B8ZS/HDB3 encoder/decoder ...

Page 2

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT DESCRIPTION The IDT82V2048 is a single chip, 8-channel T1/E1 short haul PCM transceiver with a reference clock of 1.544 MHz (T1) or 2.048 MHz (E1). The IDT82V2048 contains 8 transmitters and 8 ...

Page 3

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RCLK TCLK RCLK RDP TDP RDP RDN TDN RDN VDDT VDDT VDDT TRING ...

Page 4

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 1 PIN DESCRIPTION Table-1 Pin Description Pin No. Name Type TQFP144 TTIP0 45 TTIP1 52 TTIP2 57 TTIP3 64 TTIP4 117 TTIP5 124 TTIP6 129 TTIP7 136 Analog Output TRING0 46 TRING1 ...

Page 5

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TD0/TDP0 37 TD1/TDP1 30 TD2/TDP2 80 TD3/TDP3 73 TD4/TDP4 108 TD5/TDP5 101 TD6/TDP6 8 TD7/TDP7 1 I BPVI0/TDN0 38 BPVI1/TDN1 31 BPVI2/TDN2 79 ...

Page 6

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 RD0/RDP0 40 RD1/RDP1 33 RD2/RDP2 77 RD3/RDP3 70 RD4/RDP4 111 RD5/RDP5 104 RD6/RDP6 5 RD7/RDP7 O 142 CV0/RDN0 High-Z 41 CV1/RDN1 34 CV2/RDN2 ...

Page 7

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 I MODE2 11 (Pulled to VDDIO/2) MODE1 I 43 MODE0/CODE CS/JAS 87 (Pulled to VDDIO/2) PBGA160 Hardware/Host Control Interface MODE2: ...

Page 8

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TS2/SCLK ALE/AS TS1/RD/R TS0/SDI/WR PBGA160 TS2: Template Select 2 In hardware control mode, the signal on ...

Page 9

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 SDO/RDY/ACK INT Open 82 Drain LP7/D7/AD7 28 LP6/D6/AD6 27 LP5/D5/AD5 I/O 26 LP4/D4/AD4 25 LP3/D3/AD3 24 LP2/D2/AD2 High-Z 23 LP1/D1/AD1 ...

Page 10

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 A4 12 MC3/A3 13 MC2/ MC1/A1 15 MC0/ 114 CLKE I 115 I TRST 95 Pull-up I TMS ...

Page 11

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 O TDO 98 High-Z I TDI 99 Pull-up 17 VDDIO - 92 18 GNDIO - 91 VDDT0 44 VDDT1 53 VDDT2 56 VDDT3 ...

Page 12

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 2 FUNCTIONAL DESCRIPTION 2.1 OVERVIEW The IDT82V2048 is a fully integrated octal short-haul line interface unit, which contains eight transmit and receive channels for use in either applications. The ...

Page 13

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn TRINGn Note: The grey blocks are bypassed and the dotted blocks are selectable. RTIPn RRINGn Peak Detector TTIPn TRINGn Table-2 System Interface Configuration (In Hardware Mode) Pin ...

Page 14

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-3 System Interface Configuration (In Host Mode) Pin MCLK Pin TDNn CRSn in e-CRS Clocked High 0 Clocked Pulse 0 Clocked Pulse 0 Clocked Pulse 1 High Pulse - Low Pulse - ...

Page 15

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 2.4.3 B8ZS/HDB3/AMI LINE CODE RULE Selectable B8ZS/HDB3 and AMI line coding/decoding is provided when the device is configured in single rail mode. B8ZS rules for T1 and HDB3 rules for E1 are ...

Page 16

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-7 AIS Condition ITU G.775 for E1 (Register LAC defaulted to ‘0’) Less than 3 zeros contained in each of two AIS Detected consecutive 512-bit stream are received 3 or more zeros ...

Page 17

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RCLKn RTIPn 1 RRINGn 2 RDn CVn RCLKn RTIPn RRINGn RDn CVn Figure-9 HDB3 Code Violations & Two BPV Detections 2.4.6.3 EXZ AND BPV DETECTION IN B8ZS B8ZS ...

Page 18

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RCLKn RTIPn 2 RRINGn 1 3 RDn CVn RCLKn RTIPn RRINGn RDn CVn 2.5 TRANSMITTER In transmit path, data in NRZ format are clocked into the device on TDn and encoded by ...

Page 19

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 Time (ns) Figure-12 DSX-1 Waveform Template Table-9 Built-in Waveform Template Selection TS2 TS1 TS0 Service ...

Page 20

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-11 Output Jitter Specification T1 AT&T Pub 62411 GR-253-CODE TR-TSY-000009 2.7 LINE INTERFACE CIRCUITRY The transmit and receive interface RTIPn/RRINGn and TTIPn/ TRINGn connections provide a matched interface to the cable. 14 ...

Page 21

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 2.9 POWER DRIVER FAILURE MONITOR An internal power Driver Failure Monitor (DFMON), parallel connected with TTIPn and TRINGn, can detect short circuit failure between TTIPn and TRINGn pins. Bit SCPB in register ...

Page 22

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 2.17.4 DUAL LOOPBACK Dual Loopback mode is set by setting bit DLBn in register DLB and bit RLBn in register RLB to ‘1’. In this configuration, after passing the encoder, the data ...

Page 23

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn Peak Detector TTIPn Driver TRINGn LOS Detector CLK&Data Jitter Slicer Recovery Attenuator (DPLL) Line Waveform Jitter Shaper Driver ...

Page 24

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn TRINGn RTIPn RRINGn TTIPn TRINGn 2.17.6 INBAND LOOPBACK Inband Loopback is a function that facilitates the system remote diagnosis. When this function is enabled, the chip will ...

Page 25

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT are configured properly. The required sequence for configuring the Inband Loopback Generator is: First, set registers e-LBAC and e-LBDC, followed by register e-LBCF. Then, to select the Inband Loopback generator set registers ...

Page 26

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 2.19 INTERRUPT HANDLING 2.19.1 INTERRUPT SOURCES There are four kinds of interrupt sources: 1. Status change in register LOS. The analog/digital loss of signal detector continuously monitors the received signal to update ...

Page 27

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn TTIPn TRINGn G.772 Monitor RTIP0 RRING0 TTIP0 TRING0 LOS Detector CLK&Data Slicer Recovery (DPLL) Peak Detector Line Waveform Driver Shaper Transmit All Ones LOS Detector CLK&Data Slicer Recovery (DPLL) Peak ...

Page 28

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 3 PROGRAMMING INFORMATION 3.1 REGISTER LIST AND MAP There are 23 primary registers (including an Address Pointer Control Register and 16 expanded registers in the device). Whatever the control interface is, 5 ...

Page 29

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-16 Expanded (Indirect Address Mode) Register List Address Hex Serial Interface A7-A1 Parallel Interface A7-A0 00 XX00000 01 XX00001 02 XX00010 03 XX00011 04 XX00100 05 XX00101 06 XX00110 07 XX00111 08 ...

Page 30

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-17 Primary Register Map Address Register R/W Bit 7 Default 00H Default 0 01H ALB 7 ALB R/W R/W Default 0 02H RLB 7 RLB R/W R/W ...

Page 31

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-17 Primary Register Map (Continued) Address Register R/W Bit 7 Default 10 Hex - TSIA R/W R/W Default 0 11 Hex - TS R/W R/W Default 0 12 Hex ...

Page 32

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-18 Expanded (Indirect Address Mode) Register Map Address Register R/W Bit 7 Default 00H SING 7 e-SING R/W Default 01H CODE 7 e-CODE R/W Default 02H CRS 7 e-CRS R/W Default 03H ...

Page 33

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 3.2 REGISTER DESCRIPTION 3.2.1 PRIMARY REGISTERS ID: Device ID Register (R, Address = 00H) Symbol Position Default An 8-bit word is pre-set into the device as the identification and revision number. This ...

Page 34

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT DFI: Driver Fault Interrupt Status Register (R, Address = 09H) Symbol Position Default 0 = (Default). Or after a DF read operation. DFI[7:0] DFI.7-0 00H 1 = Any transition on DFn (Corresponding ...

Page 35

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT GCF: Global Configuration Register (R/W, Address = 0FH) Symbol Position Default 0 = Normal operation. - GCF Reserved AIS insertion to the system side disabled on LOS. ...

Page 36

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT AIS: Alarm Indication Signal Status Register (R, Address = 13H) Symbol Position Default 0 = Normal operation. (Default) AIS[7:0] AIS.7-0 00H 1 = AIS detected. AISM: Alarm Indication Signal Interrupt Mask Register ...

Page 37

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 3.2.2 EXPANDED REGISTER DESCRIPTION e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00H) Symbol Position Default 0 = Pin TDNn selects single rail mode or dual rail mode. (Default) SING[7:0] ...

Page 38

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT e-LBCF: Inband Loopback Configuration Register Symbol Position Default 0 = Normal Operation. (Default) - LBCF.7 Reserved. Loopback Detector Enable LBDE LBCF Inband loopback code detection is ...

Page 39

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT e-LBI: Inband Loopback Interrupt Status Register (R, Expanded Address = 0DH) Symbol Position Default 0 = (Default). Or after a read of e-LBS operation. LBI[7:0] LBI.7-0 00H 1 = Any transition on ...

Page 40

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 4 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2048 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction ...

Page 41

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-19 Instruction Register Description IR Code Instruction The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is ...

Page 42

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 16 PIOS N/A 17 TCLK1 TCLK1 18 TDP1 TDP1 19 TDN1 TDN1 20 RCLK1 RCLK1 21 RDP1 RDP1 22 RDN1 ...

Page 43

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 57 MODE0 MODE0 58 TCLK5 TCLK5 59 TDP5 TDP5 60 TDN5 TDN5 61 RCLK5 RCLK5 62 RDP5 RDP5 63 RDN5 ...

Page 44

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT 4.3 TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. 26 shows its state diagram A description of each state follows. Note that the figure contains two main ...

Page 45

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Table-22 TAP Controller State Description (Continued) State This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter ...

Page 46

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT ABSOLUTE MAXIMUM RATING Symbol VDDA, VDDD Core Power Supply VDDIO0, VDDIO1 I/O Power Supply VDDT0-7 Transmit Power Supply Input Voltage, any digital pin Vin Input Voltage ESD Voltage, any pin Transient Latch-up ...

Page 47

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT POWER CONSUMPTION Symbol E1, 3 Ω Load 50% ones density data: 100% ones density data: E1, 3.3 V, 120 Ω Load 50% ones density data: 100% ones density data: E1, ...

Page 48

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TRANSMITTER CHARACTERISTICS Symbol V (1) Output Pulse Amplitudes o-p E1, 75 Ω load E1, 120 Ω load T1, 100 Ω load V Zero (space) Level O-S E1, 75 Ω load E1, 120 ...

Page 49

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RECEIVER CHARACTERISTICS Symbol ATT Permissible Cable Attenuation (E1: @ 1024 kHz, T1: @ 772 kHz) IA Input Amplitude SIR Signal to Interference Ratio Margin SRE Data Decision Threshold (refer to peak input ...

Page 50

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER ATTENUATOR CHARACTERISTICS Symbol f Jitter Transfer Function Corner Frequency (–3 dB) -3dB Host mode Hardware mode Jitter Attenuator ( 400 Hz @ ...

Page 51

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TRANSCEIVER TIMING CHARACTERISTICS Symbol MCLK Frequency E1: T1: MCLK Tolerance MCLK Duty Cycle Transmit Path TCLK Frequency E1: T1: TCLK Tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data ...

Page 52

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TCLKn TDn/TDPn BPVIn/TDNn RCLKn RDn/RDPn (CLKE = 1) CVn/RDNn RDn/RDPn (CLKE = 0) CVn/RDNn t1 Figure-27 Transmit System Interface Timing Figure-28 Receive System Interface Timing 52 ...

Page 53

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JTAG TIMING CHARACTERISTICS Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to ...

Page 54

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PARALLEL HOST INTERFACE TIMING CHARACTERISTICS INTEL MODE READ TIMING CHARACTERISTICS Symbol t1 Active RD Pulse Width t2 Active CS to Active RD Setup Time t3 Inactive RD to Inactive CS Hold Time ...

Page 55

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT CS RD ALE(=1) A[4:0] D[7:0] RDY INT CS RD ALE AD[7:0] RDY INT t2 t1 t13 ADDRESS t6 t8 t15 Figure-30 Non-Multiplexed Intel Mode Read Timing t2 t1 t11 t12 t13 t16 ...

Page 56

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT INTEL MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active WR Pulse Width t2 Active CS to Active WR Setup Time t3 Inactive WR to Inactive CS Hold Time t4 Valid Address to Latch ...

Page 57

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT MOTOROLA MODE READ TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active ...

Page 58

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT MOTOROLA MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active ...

Page 59

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT SERIAL HOST INTERFACE TIMING CHARACTERISTICS Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time t5 CS ...

Page 60

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER TOLERANCE PERFORMANCE E1 JITTER TOLERANCE PERFORMANCE G.823 IDT82V2048 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TOLERANCE PERFORMANCE AT&T62411 IDT82V2048 Test condition: QRSS; Line code rule B8ZS ...

Page 61

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER TRANSFER PERFORMANCE E1 JITTER TRANSFER PERFORMANCE G.736 IDT82V2048 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TRANSFER PERFORMANCE AT&T62411 GR-253-CORE TR-TSY-000009 IDT82V2048 Test condition: QRSS; Line code ...

Page 62

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT ORDERING INFORMATION XXXXXXX Device Type DATASHEET DOCUMENT HISTORY 11/04/2001 pgs 11, 19 11/20/2001 pgs 12, 14, 18, 19, 27, 30, 36, 44, 45, 46, 58 11/28/2001 pgs. 5, ...

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