82V2048DA IDT, Integrated Device Technology Inc, 82V2048DA Datasheet - Page 26

• Manufacturer Part Number: 82V2048DA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DA

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
2.19 INTERRUPT HANDLING
2.19.1 INTERRUPT SOURCES
There are four kinds of interrupt sources:
1. Status change in register LOS. The analog/digital loss of signal
2. Status change in register DF. The automatic power driver circuit
3. Status change in register AIS. The AIS detector monitors the
4. Status change in register e-LBS. The IBLC detector monitors
detector continuously monitors the received signal to update the
specific bit in register LOS which indicates presence or absence
of a LOS condition.
continuously monitors the output drivers signal to update the
specific bit in register DFM which indicates presence or absence
of an output driver short circuit condition.
received signal to update the specific bit in register AIS which
indicates presence or absence of a AIS condition.
the inband loopback activation or deactivation code in received
signal to update the specific bit in register e-LBS which indicates
presence or absence of an inband loopback condition.
Figure-23 Interrupt Service Routine
No
Read Interrupt Status Register
Read Corresponding Status
Service the Interrupt
Interrupt Allowed
Interrupt Condition
Register
Exist?
Yes
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2.19.2 INTERRUPT ENABLE
four kinds of interrupts are all reported by this pin. When the Interrupt
Mask register (LOSM, DFM, AISM and e-LBM) is set to ‘1’, the Interrupt
Status register (LOSI, DFI, AISI and e-LBI) is enabled respectively.
Whenever there is a transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corresponding
status register, the Interrupt Status register will change into ‘1’, which
means an interrupt occurs, and there will be a high to low transition on
INT pin. An external pull-up resistor of approximately 10 kΩ is required
to support the wire-OR operation of INT. When any of the four Interrupt
Mask registers is set to ‘0’ (the power-on default value is ‘0’), the corre-
sponding Interrupt Status register is disabled and the transition on status
register is ignored.
2.19.3 INTERRUPT CLEARING
AISI and e-LBI, are read to identify the interrupt source. These registers
will be cleared to ‘0’ after the corresponding status registers: LOS, DF,
AIS and e-LBS are read. The Status registers will be cleared once the
corresponding conditions are met.
interrupt handling in the interrupt service routine is showed in Figure-23.
2.20 G.772 MONITORING
regular transceivers. In applications using only seven channels (chan-
nels 1 to 7), channel 0 is configured to non-intrusively monitor any of the
other channels’ inputs or outputs on the line side. The monitoring is non-
intrusive per ITU-T G.772.
The receiver path or transmitter path to be monitored is configured by
pins MC[3:0] in hardware mode or by register PMON in host mode.
circuit of channel 0. The monitored clock can output on RCLK0 which
can be used as a timing interfaces derived from E1 signal. The moni-
tored data can be observed digitally at the output pins RCLK0, RD0/
RDP0 and RDN0. LOS detector is still in use in channel 0 for the moni-
tored signal.
back. The signal which is being monitored will output on TTIP0 and
TRING0. The output signal can then be connected to a standard test
equipment with an E1 electrical interface for non-intrusive monitoring.
Pin INT is pulled high when there is no pending interrupt left. The
The eight channels of IDT82V2048 can all be configured to work as
The monitored signal goes through the clock and data recovery
In monitoring mode, channel 0 can be configured in Remote Loop-
The IDT82V2048 provides a latched interrupt output (INT) and the
When an interrupt occurs, the Interrupt Status registers: LOSI, DFI,
INDUSTRIAL TEMPERATURE RANGES
Figure-24
shows the Monitoring Principle.