82V2088BBG IDT, Integrated Device Technology Inc, 82V2088BBG Datasheet - Page 28

• Manufacturer Part Number: 82V2088BBG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2088BBG

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.6
Activate/Deactivate Loopback Code) will be generated and detected by the
IDT82V2088. TCLKn is used as the reference clock by default. MCLK can
also be used as the reference clock by setting the PATT_CLK bit (MAINT0,
0AH...) to ‘1’.
(MAINT0, 0AH...) are set to ‘00’, the transmit path will operate in normal
mode.
3.6.1
stream when the PATT[1:0] bits (MAINT0, 0AH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT0, 0AH...).
3.6.2
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0AH...) are set to ‘00’.
3.6.3
in the receive direction by IDT82V2088. The QRSS is 2
cations and the PRBS is 2
restrictions according to the AT&T TR62411 and ITU-T O.151.
QRSS pattern will be inserted into the transmit data stream with the MSB
first. The PRBS/QRSS pattern will be transmitted directly or invertedly.
PRBS/QRSS has reached synchronization status, the PRBS_S bit
(STAT0, 14H...) will be set to ‘1’, even in the presence of a logic error rate
less than or equal to 10
are shown in Table-20.
Table-20 Criteria for Setting/Clearing the PRBS_S Bit
PRBS/QRSS
Detection
PRBS/QRSS
Missing
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and
If the PATT_CLK bit (MAINT0, 0AH...) is set to ‘0’ and the PATT[1:0] bits
In transmit direction, the All Ones data can be inserted into the data
If the PATT_CLK bit (MAINT0, 0AH...) is set to ‘1’, the All Zeros will be
A PRBS/QRSS will be generated in the transmit direction and detected
When the PATT[1:0] bits (MAINT0, 0AH...) are set to ‘10’, the PRBS/
The PRBS/QRSS in the received data stream will be monitored. If the
TRANSMIT AND DETECT INTERNAL PATTERNS
TRANSMIT ALL ONES
TRANSMIT ALL ZEROS
PRBS/QRSS GENERATION AND DETECTION
6 or less than 6 bit errors detected in a 64 bits hopping window.
More than 6 bit errors detected in a 64 bits hopping window.
-1
. The criteria for setting/clearing the PRBS_S bit
15
-1 for E1 applications, with maximum zero
20
-1 for T1/J1 appli-
28
0AH...).
16H...). The PRBS_IES bit (INTES, 13H...) can be used to determine
whether the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS
bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IM bit
(INTM0, 11H...) is set to ‘1’.
counter if the ERR_SEL [1:0] bits (MAINT6, 10H...) are set to ‘00’. Refer to
Refer to
operation of the error counter.
3.7
ferent loopback configurations: Analog Loopback, Digital Loopback,
Remote Loopback and Inband Loopback.
3.7.1
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. At the same time, the
transmit signals are still output to TTIPn/TRINGn in transmit direction.
ure-15
3.7.2
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion.
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
3.7.3
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path.
PRBS data can be inverted through setting the PRBS_INV bit (MAINT0,
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
The received PRBS/QRSS logic errors can be counted in a 16-bit
To facilitate testing and diagnosis, the IDT82V2088 provides four dif-
When the ALP bit (MAINT1, 0BH...) is set to ‘1’, the corresponding chan-
When the DLP bit (MAINT1, 0BH...) is set to ‘1’, the corresponding chan-
Both Analog Loopback mode and Digital Loopback mode allow the
When the RLP bit (MAINT1, 0BH...) is set to ‘1’, the corresponding chan-
Figure-16
shows the process.
LOOPBACK
ANALOG LOOPBACK
DIGITAL LOOPBACK
REMOTE LOOPBACK
3.8 ERROR DETECTION/COUNTING AND INSERTION
Figure-17
shows the process.
shows the process.
TEMPERATURE RANGES
INDUSTRIAL
for the
Fig-