DJLXT384LE.B1SE001 Intel, DJLXT384LE.B1SE001 Datasheet - Page 74

• Manufacturer Part Number: DJLXT384LE.B1SE001
• Manufacturer: Intel

Specifications of DJLXT384LE.B1SE001

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Intel
7.5
7.5.1
7.5.2
7.5.3
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LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Note:
Interrupt Handling
Interrupt Sources
Interrupt sources include the following:
Interrupt Enable
The LXT384 Transceiver provides a latched interrupt output (INT). An interrupt occurs any time
there is a transition on any enabled bit in the corresponding status register.
Register 06h
Interrupt Enable register. Writing a logic ‘1’ into the corresponding mask register enables a bit in
the corresponding interrupt status register to generate an interrupt. The power-on default value is
all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers.
Register 08h
Interrupt Status register. When there is a transition on any enabled bit in a status register, the
associated bit of the interrupt status register is set and an interrupt is generated (if one is not already
pending). When an interrupt occurs, the INT pin is asserted low. The output circuitry of the INT pin
consists of an active pull-down device (an open drain). An external pull-up resistor of
approximately 10kΩ is required to support wired-OR operation with other LXT384 Transceivers.
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) operates as follows:
1. Status change in the LOS (Loss of Signal) Status register (04h,
2. Status change in the AIS (Alarm Indication Signal) Status register (13h,
1. The ISR must read the interrupt status registers (08h and 15h) to identify the interrupt source.
2. The ISR must then read the corresponding status monitor register to obtain the current status of
•
•
Transceiver continuously monitors the receiver signal and updates the specific LOS status bit
to indicate either the presence or absence of an LOS condition.
(Loss of Signal) Status register (04h,
Table
specific AIS status bit to indicate either the presence or absence of a AIS condition.
the LXT384 Transceiver.
Reading an interrupt-status register clears the ‘sticky’ status bit set by the interrupt. (A ‘sticky’
status bit is a bit that, once set, remains set until it is explicitly cleared.) Automatically clearing
an interrupt-status register prepares the register for the next interrupt.
The status-monitor registers are the LOS Status register (04h,
register (13h,
on the rising edge of the read or data strobe. When all pending interrupts are cleared, the signal
on INT goes high.
32). The LXT384 Transceiver monitors the incoming data stream and updates the
(Table
(Table
Table
36) is the LOS Interrupt Status register, and register 15h
34) is the LOS Interrupt Enable register, and register 14h
47). Reading a status-monitor register clears its corresponding interrupts
Table
32). The LOS (Loss of Signal) Status register (04h,
Table
Table
Revision Date: November 28, 2005
32)and the AIS Status
32). The LXT384
(Table
Table
(Table
Document Number: 248994
Revision Number: 005
49) is the RAIS
47). The LOS
48) is the AIS