DJLXT384LE Intel, DJLXT384LE Datasheet
DJLXT384LE
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DJLXT384LE Summary of contents
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... By changing the LXT384 Transceiver output transformer ratio from 1:2 to 1:1.7, the savings occur whether TVCC 3.3 V. 130 mW per channel (typical). See ® Table 63 “Intel LXT384 Transceiver Power Consumption” on page 104 and 3 Table 64 “Load Power Consumption” ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725 visiting Intel's website at http://www.intel.com. ...
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... Clocks and Clock-Related Signals ...................................................................... 37 5.6 Configuration and Mode-Select Signals .............................................................. 39 5.7 Signal Loss and Line-Code-Violation Signals ..................................................... 41 5.8 Power and Grounds ............................................................................................43 5.9 Test Signals......................................................................................................... 44 ® 5.10 Intel LXT384 Transceiver Line Length Equalizers.............................................45 6.0 Functional Description 6.1 Functional Overview ............................................................................................47 6.2 Initialization and Reset ........................................................................................ 47 6.3 Receiver .............................................................................................................. 48 6.3.1 Receiver Clocking ...
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... Electrical Characteristics 11.0 Timing Characteristics ® 11.1 Intel LXT384 Transceiver Timing .................................................................... 106 11.2 Host Processor Mode - Parallel Interface Timing.............................................. 109 11.2.1 Intel 11.2.2 Motorola* Processor - Parallel Interface Timing................................... 115 11.3 Host Processor Mode - Serial Interface Timing ................................................ 121 4 ................................................................................... 69 ............................................................................................. 86 ...................................................................................... 96 ......................................................................................... 105 ® ...
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... Intel LXT384 Transceiver Remote Loopback ....................................................64 11 TAOS Data Path for Intel 12 TAOS with Analog Loopback for Intel 13 TAOS with Digital Loopback for Intel 14 Host Processor Mode - Serial Interface Read Timing ......................................... 73 15 JTAG Architecture ............................................................................................... 86 16 JTAG State Diagram ........................................................................................... 88 17 Analog Test Port Application ............................................................................... 93 18 JTAG Timing ...
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... Dimensions for 160-Ball Plastic Ball Grid Array (BGA) ..................................... 134 38 Sample LQFP Non-RoHS Package - Intel 39 Sample LQFP RoHS Package - Intel 40 Sample Plastic BGA Non-RoHS Package - Intel 41 Sample Plastic BGA RoHS Package - Intel 42 Order Matrix ...................................................................................................... 138 6 ® LXT384 Transceiver ..................... 135 ® LXT384 Transceiver............................. 135 ® ...
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... LOS Status Monitor Register, LOS - 04h ............................................................ 79 33 DFM Status Monitor Register, DFM (05h) for Intel 34 LOS Interrupt Enable Register, LIE - 06h............................................................ 79 35 DFM Interrupt Enable Register, DIE (07h) for Intel 36 LOS Interrupt Status Register, LIS - 08h............................................................. 79 37 DFM Interrupt Status Register, DIS (09h) for Intel 38 Reset Register, RES - 0Ah ...
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... Line-Interface-Unit Circuit Specifications .......................................................... 123 ® 73 Intel LXT384 Transceiver Transformer Specifications .................................... 123 74 ITU G.703 2.048 Mbit/s Pulse Mask Specifications .......................................... 124 75 T1.102 1.544 Mbit/s Pulse Mask Specifications for Intel ® 76 Intel LXT384 Transceiver Jitter Attenuator Characteristics............................. 126 ® 77 Intel LXT384 Transceiver Analog Test Port Characteristics ........................... 127 78 Product Ordering Information ...
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... Changed text in 135 Added RoHS package information, starting at Page Number 24 Table 7 “Microprocessor-Standard Bus and Interface Table 45 “Pulse Shaping Data Register, PSDAT (11h) for Intel® LXT384 84 to footnotes. Page Number Major editing/rewriting/reorganizing, based on results of extensive testing of this device, and on - customer feedback about how the device is actually used. ...
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Contents 10 Datasheet Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ...
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... Introduction to this Document 1.1 Audience and Purpose The audience for this document is design engineers. The purpose of this document is to provide design information about the Intel Short-Haul Pulse-Code Modulation Transceiver with Jitter Attenuation (called hereafter the LXT384 Transceiver). The rest of this document is organized as follows: • ...
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... LXT384/6/8 Frequently Asked Questions ® Intel LXT384/6/8 Twisted Pair Interface - Without Component Changes - Application Note ® Intel LXT384/6/8 Universal 75/100/120 Ohm Interface T1/E1/J1, N+1 Redundancy with Analog Switches and Intel Preliminary Application Note Transformer Specification for Intel 12 ® LXT385 Transceiver and the Intel ® ...
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... ITU G.772. ® Intel Hitless Protection Switching. The LXT384 Transceiver can operate in an Intel Protection Switching mode, which uses one transceiver to back up another, in case the primary transceiver fails. This method is often referred to as 1+1 redundancy protection. Typical redundancy methods used external relays ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure high-level block diagram of the LXT384 Transceiver. ® Figure 1. Intel LXT384 Transceiver High-Level Block Diagram JTAG Serial/ Parallel Port RTIP RRING TTIP TRING JA = Jitter Attenuator JTAG = Joint Test Action Group * LOS = Loss of Signal. (LOS Detector is used in data-recovery operations.) ...
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... Figure detailed block diagram of the LXT384 Transceiver. . ® Figure 2. Intel LXT384 Transceiver Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT Transceiver 7 RTIP7 RRING7 TTIP7 TRING7 RTIP6/RRING6 TTIP6/TRING6 RTIP5/RRING5 Transceiver 5 TTIP5/TRING5 Transceiver 4 RTIP4/RRING4 TTIP4/TRING4 RTIP3/RRING3 Transceiver 3 TTIP3/TRING3 RTIP2/RRING2 Transceiver 2 TTIP2/TRING2 RTIP1/RRING1 Transceiver 1 TTIP1/TRING1 ...
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... A 144-pin Low-Profile Octal-Flat Package, or ‘LQFP’ • A 160-ball Plastic Ball Grid Array package, or ‘PBGA’ ® Table 2. Intel LXT384 Transceiver Package Top-Side Markings Marking Part Number Number of the unique identifier for this product family Lot Number A lot (that is, ‘batch’) number ...
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... Figure 3 shows a top view of the LXT384 Transceiver Low-profile Octal Flat Pack (LQFP) package, with pin assignments. For package information, see Information”. ® Figure 3. Intel LXT384 Transceiver 144-Pin Assignments 1 TCLK7 2 LOS6 3 TPOS7/TDATA7 1 4 TCLK7 2 5 LOS6 RCLK6 3 6 RNEG6/BPV6 4 7 RPOS6/RDATA6 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 4 shows a bottom view of the LXT384 Transceiver PBGA package and the pin assignments. ® Figure 4. Intel LXT384 Transceiver Plastic Ball Grid Array (PBGA) Pin Assignments RCLK RPOS RNEG TVCC TCLK TPOS TNEG ...
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... Host Processor mode with a parallel interface and the MOT/INTL pin is: — Low, Column 2 names and functions apply to a Motorola processor with a parallel interface. — High, Column 3 names and functions apply to an Intel interface. • Host Processor mode with a serial interface, Column 4 names and functions apply to either a ...
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... R/W Read/write RD enable Address Address AS ALE latch strobe enable Data Write DS WR strobe enable Data transfer ACK RDY Ready acknow- ledge 4. Serial Interface - ® Motorola or Intel Processor Signal Signal Name Function No A4 connect connect A0 CODEN/ INTL / No MOT connect Chip CS select Must ...
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... RCLK2 32 M1 RCLK1 39 P1 RCLK0 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA and Section 5.3.2, “Bipolar vs. Unipolar Operation - 28. Bipolar I/O Signal Functions Receive negative data BPV7 output BPV6 BPV5 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 6 lists LXT384 Transceiver transmitter pins that have different names and functions depending on the I/O mode selected. Table 6. Transmitter Bipolar/Unipolar I/O Signal Functions Pins Balls 144 B3 TNEG7 7 D3 TNEG6 102 D12 TNEG5 ...
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... Section 5.8, “Power and Grounds” • Section 5.9, “Test Signals” Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Chapter 3.0, “Pin Assignments and Package” Specifications”.) and 23 ...
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... DI Address Latch Enable Input. When the LXT384 Transceiver is in the: • Host Processor mode using an Intel interface, ALE acts as an address latch enable. In this case, the address on the multiplexed address/data bus pins D7:0 (also called AD7:0) is clocked into the LXT384 Transceiver with the falling edge of ALE. • ...
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... INT requires an external 10kΩ pull-up resistor. J13 DI Read Enable (Active Low) Input. When the LXT384 Transceiver is in the: • Host Processor mode using an Intel functions as a read enable. • Hardware mode, RD must be connected to ground. For other pin functions, see R/W. Signals”.) Table 34 ...
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... For other pin functions, see ACK and RDY. J14 DI Write Enable Input. When the LXT384 Transceiver is in: • Host Processor mode using an Intel a write enable. • Hardware mode, WR must be connected to ground. For other pin functions, see DS and SDI. ® processor, WR acts as ...
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... RDATA validation relative to RCLK is selectable with CLKE pin polarity. See the CLKE pin description in Table 11, “Clocks and Clock-Related Signals” on page Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 8 Table 11, “Clocks and Clock-Related Signals” on page lists details. 37. 37. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 5.3.2 Bipolar vs. Unipolar Operation - Transmit Side Table 6 on page 22 lists transmit-side framer/mapper signals, which connect to a framer/mapper using either bipolar or unipolar interface connections. • TDATA - works in combination with BPV outputs, in unipolar mode. ...
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... AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA lists and describes the LXT384 Transceiver framer/mapper transmit blue bold print indicates the signal being discussed. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 8. Framer/Mapper Receive Signals (Sheet Signal Name BPV7 / RNEG7 BPV6 / RNEG6 BPV5 / RNEG5 BPV4 / RNEG4 BPV3 / RNEG3 BPV2 / RNEG2 BPV1 / RNEG1 BPV0 / RNEG0 RDATA7 / RPOS7 RDATA6 / RPOS6 RDATA5 / RPOS5 RDATA4 / RPOS4 RDATA3 / ...
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... Signal Name TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA QFP PBGA Signal Pin Ball Type Transmit Clock Input 7: When the LXT384 Transceiver is in Hardware mode and ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 9. Framer/Mapper Transmit Signals (Sheet Signal Name TNEG7 / UBS7 TNEG6 / UBS6 TNEG5 / UBS5 TNEG4 / UBS4 TNEG3 / UBS3 TNEG2 / UBS2 TNEG1 / UBS1 TNEG0 / UBS0 TNEG7 / UBS7 TNEG6 / UBS6 TNEG5 / UBS5 TNEG4 / UBS4 TNEG3 / ...
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... TDATA4 / TPOS4 TDATA3 / TPOS3 TDATA2 / TPOS2 TDATA1 / TPOS1 TDATA0 / TPOS0 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA QFP PBGA Signal Pin Ball Type Transmit Positive Data Input 7: For the TPOS description, see TNEG. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 5.4 Line Interface Unit Signals For multi-function pins, the pin name in Table 10. Line Interface Unit Signals (Sheet Signal QFP Name Pin D7 / LOOP7 LOOP6 LOOP5 LOOP4 LOOP3 LOOP2 LOOP1 LOOP0 21 1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. ...
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... TRING1 51 TRING0 46 1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA PBGA Signal Signal Description Ball Type E14 DI Output Driver Enable Input ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 10. Line Interface Unit Signals (Sheet Signal QFP Name Pin TTIP7 136 TTIP6 129 TTIP5 124 TTIP4 117 TTIP3 64 TTIP2 58 TTIP1 52 TTIP0 45 1. AI: Analog Input. AO: Analog Output. DI: Digital Input. DI/O: Digital Bidirectional Port. DO: Digital Output. ...
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... Mode”), the output polarity on both RDATA or RPOS and RNEG is: • Active-low when CLKE is low. • Active-high when CLKE is high Signal Description Section 6.3.1, “Receiver Clocking”), setting Figure 20 in Section 19, “Intel® LXT384 Timing”.) Figure 20 in Section 19, “Intel® LXT384 Timing”.) SCLK for Valid SDO SCLK SCLK 37 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 11. Clocks and Clock-Related Signals (Sheet Signal QFP PBGA Name Pin Ball MCLK 10 RCLK SCLK TCLK 1. DI: Digital Input 38 Signal Type E1 DI Master Clock Input. MCLK is an independent, free-running reference clock that must be used at 1 ...
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... DI Host Processor Select Input. When the LXT384 Transceiver is in the host processor mode and this signal is: • high, the host processor interface is configured for Intel microcontrollers. • low, the host processor interface is configured for Motorola microcontrollers. For other pin functions, see CODEN. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 12. Configuration and Mode-Select Signals (Sheet Signal QFP Name Pin MODE 11 MUX 43 TNEG7 / UBS7 144 TNEG6 / UBS6 7 TNEG5 / UBS5 102 TNEG4 / UBS4 109 TNEG3 / UBS3 72 TNEG2 / UBS2 79 TNEG1 / UBS1 31 TNEG0 / UBS0 38 1. DI: Digital Input ...
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... LOS2 75 LOS1 35 LOS0 42 RCLK7:0 1. DI: Digital Input. DO: Digital Output. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA PBGA 1 I/O Ball F4 DI Performance Monitoring Input. F3 When the LXT384 Transceiver is in the: F2 • ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 14 lists performance-monitoring selections that can be made when the LXT384 Transceiver is in the Hardware mode. Table 14. Performance-Monitoring Selections with A3:0 Pins Signal QFP PBGA Name Pin Ball Signal Description Performance Monitoring Input. ...
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... VCC0 19 VCCIO1 92 VCCIO0 Ground. P: Power. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA PBGA Signal Ball Type H11 G Ground (Core) 1: GND0 and GND1 pins are ground for the digital core. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 5.9 Test Signals Table 17 lists and describes the LXT384 Transceiver test signals, which are used to test all digital input, output, and input/output pins. The JTAG test signals are compatible with the IEEE 1149.1 boundary-scan test. ...
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... In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of pulse output at TTIP/TRING. Refer to ® Table 18. Intel LXT384 Transceiver Line Length Equalizers Signal QFP Name Pin LEN0 84 LEN1 85 LEN2 86 ® Table 19. Intel LXT384 Transceiver Line Length Equalizer Inputs LEN2 LEN1 LEN0 ...
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... Section 6.6, “Jitter Attenuation” • Section 6.7, “Loopbacks” • Section 6.8, “Transmit All Ones Operations” • Section 6.9, “Performance Monitoring” • Section 6.10, “Intel® Hitless Protection Switching” 46 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ...
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... Section 1.3, “Related 2. A write to the reset register (RES, LXT384 Transceiver registers to their default values. When the reset cycle occurs: ® the Intel b. In all other modes, the reset cycle is 1 microsecond long. Note: For more information related to reset, see Interface”. ...
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... The peak detector sends a percentage of the maximum peak value to the data slicers. This percentage acts as a threshold level to ensure an optimum signal-to-noise ratio. The threshold level is typically 50% for E1 applications (see Receive Transmission Characteristics” on page Table 64, “Intel® LXT384 Transceiver T1 Receive Transmission Characteristics” on page 104). 48 and Section 6.3.1, “ ...
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... The incoming signal is considered to have transitions when the signal level is equal or greater than 250 mV. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 33, “Intel® LXT384 Transceiver 128. Register). 49 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 6.3.4 Receiver Data Recovery Mode In data-recovery mode, the combined analog/digital LOS detector circuit uses only its LOS analog part, which complies with the ITU-G.775 recommendation. The LOS digital timing is derived from an internal self-timed circuit. RPOS/RNEG stay active during the loss of signal. ...
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... Ordinarily, when successive ones are transmitted, one has a positive voltage and the other has a negative voltage. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 85) Section 6.3.3, “Receiver Loss-Of-Signal Section 5.3, “Framer/Mapper Signals”.) Table 48, “ ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 6.4 Transmitter The LXT384 Transceiver has eight identical transmitters. 6.4.1 Transmitter Clocking The eight low-power transmitters of the LXT384 Transceiver are identical. Transmit data is clocked serially into the device at TPOS/TNEG in bipolar mode TDATA in unipolar mode. ...
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... Note: The TAOS generator uses MCLK as a timing reference. To ensure that the output frequency is within specification limits, MCLK must have the applicable stability. TAOS is inhibited during Remote Loopback. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with Specifications”). Figure 5. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA In the Hardware mode, if TCLK is connected high 16 consecutive MCLK clock cycles and MCLK is: • Not supplied (or ‘low’), the transmit pulse-shaper circuit shown in is, disabled). In this case, TPOS and TNEG control the pulse width and polarity on TTIP and TRING. • ...
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... Note: If TCLK is not supplied, the transmitter powered-down state and the TTIP and TRING outputs are held in a low-power high-impedance tristate. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Specifications”.) Table 21. Figure 6 and Chapter 12 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 6.4.4 Transmitter Output Driver Power and Grounds Each output driver is supplied by its own separate TVCC and TGND pins. The TVCC pins can be either 3 nominal. The LXT384 Transceiver drives either a 75Ω coaxial cable or a 120Ω ...
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... Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Specifications”. and Schottky diodes D1-4 protect the output drivers from line T 6, add a single 0.47 uF capacitor in series with one of the R ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA ® Figure 6. Intel LXT384 Transceiver External Transmit/Receive Line Circuitry TVCC 68μF 1 0.1μF 3.3V VCC 0.1μF GND Intel Transceiver LXT384 (ONE CHANNEL) ® Intel LXT384 Transceiver 1 Common decoupling capacitor for all TVCC and TGND pins. ...
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... Low-power 75/120Ω characteristic impedance Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 6 circuit, depending on the type of Component Value to Use with Component Value to Use with 75 Ω Coaxial Cable 120 Ω ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 6.6 Jitter Attenuation Figure 7 shows the internal LXT384 Transceiver jitter attenuation (JA) unit, which requires neither an external crystal nor a reference clock that has a frequency higher than the line frequency. Data signals are clocked into the FIFO with the associated clock signal (TCLKi or RCLKi) and are clocked out of the FIFO with the JA clock after removing jitter (TCLKo when TCLKi is used, or RCLKo when RCLKi is used) ...
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... AT&T Pub 62411 • GR-25-CORE, Category I, R5-203 • TR-TSY-000009 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 43) JASEL bits determine whether the JA is “Registers”.) Performance”.) Specifications”.) Table 43 in ...
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... RTIP and RRING. For the corresponding receiver, clock and data signals are output at RCLK, RPOS, and RNEG. (For the LOOP pin settings that select analog loopback, see When the LXT384 Transceiver analog loopback, it ignores signals on RTIP and RRING. ® Figure 8. Intel LXT384 Transceiver Analog Loopback TCLK TPOS TNEG ...
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... TPOS and TNEG is also output on the TTIP and TRING pins. (To select digital loopback, see Table 40 in Chapter 8.0, When the LXT384 Transceiver digital loopback, it ignores input signals on RTIP and RRING. ® Figure 9. Intel LXT384 Transceiver Digital Loopback TCLK TPOS TNEG RCLK RPOS RNEG ...
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... When the LXT384 Transceiver remote loopback: • It ignores input signals on the TCLK, TPOS, and TNEG. • The pulse template cannot be guaranteed in data-recovery mode. ® Figure 10. Intel LXT384 Transceiver Remote Loopback TCLK TPOS TNEG RCLK RPOS ...
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... To ensure the output frequency is within specification limits, MCLK must have the applicable stability. • When TAOS is active, DLOOP does not function. Figure 11 shows how the LXT384 Transceiver generates the Transmit All Ones mode. Figure 11. TAOS Data Path for Intel MCLK TAOS mode TCLK TPOS TNEG ...
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... TPOS TNEG RCLK RPOS RNEG * If Enabled 6.8.3 TAOS Generation with Digital Loopback Figure 13 shows how the TAOS mode affects the receive path after digital loopback. Figure 13. TAOS with Digital Loopback for Intel MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 66 ® ...
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... Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Signals”) or the Host Processor mode (see in Chapter 2.0, “Product Summary”, the analog input from the channel ...
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... Intel Hitless Protection Switching The LXT384 Transceiver has a feature that allows used in an Intel Switching application. Intel method that uses very fast silicon switching instead of slow mechanical relays. This method is best implemented using 1+1 circuitry. The LXT384 Transceiver can provide Intel reasons: • ...
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... Processor interface. In the Hardware mode, the Host Processor interface pins have different functions, in that they can be hard-wired to control the LXT384 Transceiver for various operation modes and to report on the status of operations. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 69 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 7.3 Hardware Mode Settings Table 23 lists LXT384 Transceiver hardware mode settings for receive, transmit, and loopback operations. ® Table 23. Intel LXT384 Transceiver Operation Mode Summary MCLK TCLK Clocked Clocked Clocked Clocked Clocked ...
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... Control signals that the LXT384 Transceiver and host processors have in common include ACK/ RDY, ALE, CS, DS, INT, RD, R/W, and WR. An internal wait-state generator controls the ACK/ RDY handshake output signal, which is compatible with both Motorola and Intel When the processor interface selected is for a: • ...
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... Host Processor Mode - Parallel Interface, Intel ® The Intel processor interface is selected by asserting the LXT384 Transceiver MOT/INTL pin high. Both the read and write cycles require low. When the Intel • Read data from the LXT384 Transceiver, it asserts RD low while WR is held high. • ...
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... Address / Command Byte SDI R High Impedance SDO R Read operation R Write operation (SDO remains high impedance) Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Input (Write) Data Byte (Don't (Don't care) care) ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 7.5 Interrupt Handling 7.5.1 Interrupt Sources Interrupt sources include the following: 1. Status change in the LOS (Loss of Signal) Status register (04h, Transceiver continuously monitors the receiver signal and updates the specific LOS status bit to indicate either the presence or absence of an LOS condition ...
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... Registers This chapter discusses the LXT384 Transceiver registers. 8.1 Register Summary Table 25 lists LXT384 Transceiver registers by the hex address of each. ® Table 25. Intel LXT384 Transceiver Register Summary Address Mnemonic (Hex ALOOP 02 RLOOP 03 TAOS 04 LOS LIE LIS RES 0B MON LACS 0E ATS ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 26 groups the LXT384 Transceiver registers by function and lists the bit names. Table 26. Register Bit Names Register Mne- Name monic ID, Reset, and Control Registers ID ID Reset RES Global Control GCR Loopback Registers ...
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... AIS Interrupt Enable AIS Interrupt Status Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Host Processor Mode Registers Addresses Serial Interface Parallel Interface (Address from Pins A7:1) (Address from Pins A7:0) ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 8.3 Register Descriptions Table 28. ID Register 00h Bit Name 7:0 ID7:0 Table 29. Analog Loopback Register, ALOOP - 01h Bit Name 7:0 AL7:0 Table 30. Remote Loopback Register, RLOOP - 02h Bit Name 7:0 RL7:0 Table 31. TAOS Enable Register, TAOS - 03h ...
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... On power-up all the register bits are set to “0” and all interrupts are disabled. Table 36. LOS Interrupt Status Register, LIS - 08h Bit Name 7:0 LIS7:0 Table 37. DFM Interrupt Status Register, DIS (09h) for Intel Bit Name 7-0 DIS7-DIS0 1. On power up all register bits are set to “0”. ...
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... When using Intel processor in a non-multiplexed mode, to use this field extend the software reset cycle time to 2 microseconds. (For more information on the software reset cycle when using an Intel non-multiplexed mode, see Section 7.4.1, “Host Processor Mode - Parallel Interface”.) ...
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... A3:0 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Description Reserved. A3:0 (Performance Monitoring Select). When bits A3:0 are all ‘0’, there is no performance monitoring of receivers, and the LXT384 Transceiver is configured as an octal line transceiver without monitoring capability. • ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 40. Digital Loopback Register 0Ch Bit Name 7:0 DL7:0 Table 41. LOS/AIS Criteria Selection Register, LACS - 0Dh Bit Name 7:0 LACS7:0 Table 42. Automatic TAOS Select Register, ATS - 0Eh Bit Name 7:0 ATS7:0 82 Description Digital Loopback. • ...
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... On power-on reset, the register is set to ‘0’. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Description Reserved. Receive Alarm Indication Signal Enable. This bit controls automatic AIS insertion in the receive path when LOS occurs. ...
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... Table 44. Pulse Shaping Indirect Address Register, PSIAD (10h) 1 Bit Name 0-2 LENAD 0 power-on reset the register is set to “0”. Table 45. Pulse Shaping Data Register, PSDAT (11h) for Intel Bit Name 1 0-2 LEN 0 power-on reset the register is set to “0”. 2. Maximum cable loss at 772 KHz. ...
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... AISIS7:0 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Description Alarm Indication Signal Status Monitor. • On power-up, all AIS7:0 bits are cleared to ‘0’. • All AIS interrupts are cleared by a single read operation. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 9.0 JTAG Boundary Scan 9.1 Overview The LXT384 Transceiver supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT384 Transceiver also includes analog test port capabilities ...
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... Temporary states that can be used to terminate the scanning process. Exit2 - IR Exit2 - DR Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 16).The TAP controls whether the LXT384 Transceiver is in reset Figure 16. Description ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 88 1 SELECT- CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- SELECT- CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 0 UPDATE- Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ...
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... TPOS1 19 TNEG1 20 RCLK1 21 RPOS1 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 17. By applying a stimulus to the AT1 input, a known voltage will Bit Symbol I/O PADD0 I/O PDO0 I/O PADD1 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 51. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 22 N/A 23 RNEG1 24 LOS1 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 N/A 31 RNEG0 32 LOS0 33 MUX 34 LOS3 35 RNEG3 36 N/A 37 RPOS3 38 RCLK3 39 TNEG3 40 TPOS3 41 TCLK3 42 LOS2 ...
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... LOS7 77 RNEG7 78 N/A 79 RPOS7 80 RCLK7 81 TNEG7 82 TPOS7 83 TCLK7 84 LOS6 85 RNEG6 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Bit Symbol I WRB I RDB I ALE I CSB I MOTO I TCLK5 I TPOS5 I TNEG5 O RCLK5 O RPOS5 HIZ5 controls the RPOS5, RNEG5 and RCLK5 pins ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 51. Boundary Scan Register (BSR) (Sheet Pin Bit # I/O Type Signal 86 N/A 87 RPOS6 88 RCLK6 89 TNEG6 90 TPOS6 91 TCLK6 92 MCLK 93 MODE Bit Symbol HIZ6 controls the RPOS6, RNEG6 and RCLK6 pins. Setting - HIZ6 HIZ6 to “0” enables output on the pins. Setting HIZ6 to “1” ...
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... Figure 17. Analog Test Port Application RTIP7 RRING7 TTIP7 TRING7 RTIP6 RRING6 TTIP6 TRING6 RTIP0 1K RRING0 1K AT2 AT1 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA JTAG Port ASR Register Transceiver 7 Transceiver 6 Transceiver 0 93 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 9.4.2 Analog Port Scan Register (ASR) The ASR bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to the ASR output ...
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... TDI TDO Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Code # Comments Connects the BSR to TDI and TDO. Input pins values are loaded into the 000 BSR. Output pins values are loaded from the BSR. ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 10.0 Electrical Characteristics The tables in this chapter specify the electrical characteristics of the LXT384 Transceiver. The specifications are guaranteed by test except, where noted, by design. The minimum and maximum values listed are guaranteed over the specified recommended operating conditions. ...
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... Digital inputs are within 10% of the supply rails, and digital outputs are driving a 50-pF load the DC supply voltage rise time exceeds 25 ms, see the LXT384 Transceiver application note on slow power-up rise time referenced in Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Parameter Symbol ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 58 lists power consumption values for the LXT384 Transceiver. ® Table 58. Intel LXT384 Transceiver Power Consumption Mode TVCC E1 3. 3. 5.0V 98 Load LEN - - 75 Ω 000 - - - - 120 Ω 000 - - - - 100 Ω 101-111 ...
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... Load includes the power being dissipated in the two RT resistors, the termination resistor, cables, and transformer Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Transmit Transmit 1:2 Transformer 1:1.7 Transformer Typic ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 60 lists the DC characteristics for the LXT384 Transceiver. Table 60. DC Characteristics Parameter Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage TTIP, TRING - output current HIgh-impedance tristate leakage current ...
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... Table 61 (E1) and Table 62 ® Table 61. Intel LXT384 Transceiver E1 Transmit Transmission Characteristics Parameter 75Ω Output pulse amplitude 120Ω 75Ω Peak voltage of a space 120Ω Transmit amplitude variation with supply Difference between pulse sequences Pulse width ratio of the positive and negative ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA ® Table 62. Intel LXT384 Transceiver T1 Transmit Transmission Characteristics (Sheet Parameter Output power @ 772 KHz 2 levels @ 1544 KHz 51kHz to 102 kHz Transmit Return 102 kHz to 2.048 MHz 1 Loss 2.048 MHz to 3.072 MHz Bipolar mode ...
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... Table 63 (E1) and Table ® Table 63. Intel LXT384 Transceiver E1 Receive Transmission Characteristics Parameter Permissible cable attenuation Receiver dynamic range Signal to noise interference margin Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA ® Table 64. Intel LXT384 Transceiver T1 Receive Transmission Characteristics Parameter Permissible cable attenuation Receiver dynamic range Signal to noise interference margin Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal ...
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... Section 11.1, “Intel® LXT384 Transceiver Timing” • Section 11.2, “Host Processor Mode - Parallel Interface Timing” — Section 11.2.1, “Intel® Processor - Parallel Interface Timing” — Section 11.2.2, “Motorola* Processor - Parallel Interface Timing” • Section 11.3, “Host Processor Mode - Serial Interface Timing” ...
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... E1 TPOS/TNEG pulse width (RZ mode) TPOS/TNEG to TCLK setup time TCLK to TPOS/TNEG hold time Delay time OE Low to driver High Z Delay time TCLK Low to driver High Z Figure transmit timing diagram for the LXT384 Transceiver. ® Figure 19. Intel LXT384 Transceiver - Transmit Timing TCLK TPOS TNEG 106 Sym Min. ...
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... Table 66 lists receive timing characteristics for the LXT384 Transceiver. ® Table 66. Intel LXT384 Transceiver Receive Timing Characteristics Parameter Clock recovery capture range Receive clock duty cycle Receive clock pulse width Receive clock pulse width Low time Receive clock pulse width High time ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure receive timing diagram for the LXT384 Transceiver. ® Figure 20. Intel LXT384 Transceiver - Receive Timing RCLK RPOS RNEG CLKE = 1 RPOS RNEG CLKE = 0 108 tPW tPWH tPWL tSUR tHR tSUR tHR Document Number: 248994 ...
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... Host Processor Mode - Parallel Interface Timing This sections gives timing characteristics and timing diagrams for both Intel Motorola processors. ® 11.2.1 Intel Processor - Parallel Interface Timing Table 67 lists read timing characteristics for the Intel ® Table 67. Intel Processor - Read Timing Characteristics ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure timing diagram for the Intel multiplexed interface, and a read cycle takes place. ® Figure 21. Intel Processor Non-Multiplexed Interface - Read Timing A4:0 ALE (Connected High D7:0 INT tDRDY Tristate RDY 110 ® ...
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... Figure timing diagram for the Intel multiplexed interface, and a read cycle takes place. ® Figure 22. Intel Processor Multiplexed Interface - Read Timing tVL ALE CS RD tSALR ADDRESS AD7-AD0 INT Tristate RDY Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 68 lists write timing characteristics for the Intel ® Table 68. Intel Processor - Write Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch active to active write setup time Chip select setup time to active write ...
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... Figure timing diagram for the Intel multiplexed interface, and a write cycle takes place. ® Figure 23. Intel Processor Non-Multiplexed Interface - Write Timing A4:0 (Connected High) ALE CS WR D7:0 INT Tristate RDY Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure timing diagram for the Intel multiplexed interface, and a write cycle takes place. ® Figure 24. Intel Processor Multiplexed Interface - Write Timing ALE tVL CS WR tSALW ADDRESS AD7-AD0 INT Tristate RDY 114 ® ...
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... Minimum and maximum values are at 25 C° and are for design aid only, not guaranteed, and not subject to production testing. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Parameter Sym. t SAR ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure timing diagram for the Motorola processor in the Host Processor mode, with a non- multiplexed interface, and a read cycle takes place. Figure 25. Motorola Processor Non-Multiplexed Interface - Read Timing A4:0 ADDRESS tSAR AS (Connected High) ...
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... R/W CS tASDS DS tSAR D7-D0 ADDRESS INT ACK Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA tVAS tSCS tVDS tPDS tHAR DATA OUT tDACKP tPACK tDSAS tHRW tHCS tDZ tINT ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Table 70 lists write timing characteristics for the Motorola processor. Table 70. Motorola Processor - Write Timing Characteristics Parameter Address setup time to address strobe Address hold time to address strobe Valid address strobe pulse width R/W setup time to active data strobe ...
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... A4:0 ADDRESS tSAS AS (Connected High) tSRW R D7:0 INT ACK Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA tHAS tSCS tVDS tDACKP tHRW tHCS tSDW tHDW WRITE DATA tINT tDACK 119 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure timing diagram for the Motorola processor in the Host Processor mode, with a multiplexed interface, and a write cycle takes place. Figure 28. Motorola Processor Multiplexed Interface - Write Timing AS tSRW R/W CS tASDS DS tSAS D7-D0 ADDRESS ...
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... Host Processor Mode - Serial Interface Timing Table 71 lists serial I/O timing for a Motorola or Intel a serial interface. Table 71. Serial I/O Timing Characteristics Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time SCLK low time SCLK high time SCLK rise and fall time ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure timing diagram for serial output from the Host Processor interface. Figure 30. Serial Output Timing CLKE = SCLK CS SDO CLKE = SCLK CS SDO 122 CCH t CDZ CCH t CDZ Document Number: 248994 Revision Number: 005 ...
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... Twisted Pair Cable TRING/TTIP termination resistor R 75Ω Coaxial Cable 120Ω Twisted Pair Cable Table 73 lists specifications for transformers with which the LXT384 Transceiver is designed to operate in an LIU circuit. ® Table 73. Intel LXT384 Transceiver Transformer Specifications 2 Tx/Rx Turns Ratio TX 1:2 RX 1:2 1 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 13.0 Mask Specifications This chapter discusses the specifications for the mask into which the LXT384 Transceiver transmitter output pulses must fit. The mask specification has two parts. • Part 1 (Table 74) lists specifications on how the pulse relates to load resistance. ...
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... Table 75. T1.102 1.544 Mbit/s Pulse Mask Specifications for Intel Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes Figure 32. T1, T1.102 Mask Templates for LXT384 -0.80 -0.60 -0.40 Document Number: 248994 ...
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... Section 6.6, “Jitter Attenuation” • Table 43 in Chapter 8.0, “Registers” Table 76 lists jitter attenuator characteristics for the LXT384 Transceiver. ® Table 76. Intel LXT384 Transceiver Jitter Attenuator Characteristics Parameter E1 jitter attenuator 3dB corner frequency, host 1 mode T1 jitter attenuator 3dB corner frequency, host ...
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... Table 77. Intel LXT384 Transceiver Analog Test Port Characteristics Parameter 3 dB bandwidth Input voltage range Output voltage range Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Sym Min. Typ Max ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 33 shows the typical LXT384 Transceiver jitter tolerance. ® Figure 33. Intel LXT384 Transceiver Jitter Tolerance Performance 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 GR-499-CORE, Dec 1995 (T1 128 LXT384 typ 300 500 Hz ITU G ...
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... Figure 34 shows the typical jitter transfer performance for the LXT384 Transceiver. ® Figure 34. Intel LXT384 Transceiver Jitter Transfer Performance 0 3Hz 0 dB -10 dB -20 dB -30 dB -40 dB - -20 dB -30 dB -40 dB - Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® ...
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... Figure 35. Intel LXT384 Transceiver Output Jitter for ETSI CTR12/13 Applications 0.2 0.15 0.1 0. 100 Hz 130 Intel® LXT384 Transceiver typical, Intel® LXT385 Transceiver typical 2.5 Hz and 3 kHz 10 kHz Frequency Revision Date: November 28, 2005 100 kHz Document Number: 248994 Revision Number: 005 ...
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... O.151 Error performance measuring equipment operating at the primary rate and above (This publication specifies instruments to measure error performance in digital systems.) Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 131 ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA • Office of Telecommunications (United Kingdom) publication: OFTEL OTR-001 Short Circuit Current Requirements • Telcordia* publications. (Telcordia was formerly known as Bellcore.) — GR-253-CORE SONET Transport Systems Common Generic Criteria — GR-499-CORE Transport Systems Generic Requirements — ...
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... See Joint Electronic Devices Engineering Council (JEDEC) publications for additional specifications. Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA ° ° NOTE: All dimensions in millimeters 0.08 R. MIN. A Millimeters 1 Minimum ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Figure 37. Dimensions for 160-Ball Plastic Ball Grid Array (BGA) 160-Pin PBGA • Part Number LXT384BE • Extended Temperature Range (-40 15.00 13.00 ±0.20 4.72 ±0.10 PIN #A1 CORNER PIN #A1 ID 4.72 ±0.10 Ø1.00 (3 plcs) ...
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... LQFP non-RoHS package for the LXT384 Transceiver. Note: In contrast to Pb-Free (RoHS-compliant) LQFP packages, the non-RoHS-compliant packages do not have the “e3” symbol in the last line of the package label. Figure 38. Sample LQFP Non-RoHS Package - Intel Pin 1 Figure 39 shows a sample LQFP RoHS package for the LXT384 Transceiver. ...
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... Figure 40. Sample Plastic BGA Non-RoHS Package - Intel Pin 1 Figure 41 shows a sample plastic BGA RoHS package for the LXT384 Transceiver. Figure 41. Sample Plastic BGA RoHS Package - Intel Pin 1 136 ® LXT384 Transceiver ...
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... Product Ordering Information Table 78 lists product ordering information for the LXT384 Transceiver. Table 78. Product Ordering Information Product Number Revision DJLXT384LE.B1 WJLXT384LE.B1 FLLXT384BE.B1 ELLXT384BE.B1 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA ...
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... B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device (MAC/Framer) IXP = Network processor Intel Package Designator Pb-Free Package Leaded WB HQFP HB WJ LQFP DJ BJ ...
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... TAOS Typ. UI UIpp Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ® Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA Meaning of Abbreviation or Acronym Alarm Indication Signal Alternate Mark Inversion Bipolar 8-Zero Substitution BiPolar Violation Electro-Static Discharge Frame Check Sequence ...
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... Intel LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA 140 Document Number: 248994 Revision Number: 005 Revision Date: November 28, 2005 ...