DJLXT384LE Intel, DJLXT384LE Datasheet - Page 27

• Manufacturer Part Number: DJLXT384LE
• Manufacturer: Intel

Specifications of DJLXT384LE

• Lead Free Status / RoHS Status: Not Compliant

5.3
5.3.1
Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Note: In bipolar I/O mode, the framer/mapper is responsible for detecting any line-code violations that
Framer/Mapper Signals
Framer/mapper signals are used to interface the LXT384 Transceiver to a framer/mapper.
Bipolar vs. Unipolar Operation - Receive Side
Table 5 on page 21
using either bipolar or unipolar interface connections.
Depending on the state of a UBS7:0 pin, both the corresponding receiver and transmitter pins are
automatically set for either bipolar I/O or unipolar I/O. When a UBS pin is connected:
Receive side - Bipolar I/O. When TNEG/UBS is connected low, then bipolar I/O is selected and
RNEG/RPOS functions are selected. In this case, the signal flow occurs as follows:
appear on the line. The framer/mapper also decodes HDB3.
Receive side - Unipolar I/O. When TNEG/UBS is connected high for more than 16 consecutive
MCLK cycles, then unipolar I/O is selected and RDATA/BPV functions are active. RDATA does
not distinguish between a positive or a negative pulse on the line. In this case, the signal flow
occurs as follows:
1. The receiver routes receive analog signals from RTIP/RRING to a data recovery circuit.
2. The data recovery circuit converts the incoming line AMI signals, which consist of positive
3. The recovered clock from RTIP/RRING is output at RCLK.
4. The RNEG and RPOS data lines and the RCLK clock line connect the LXT384 Transceiver to
5. RNEG/RPOS validation relative to RCLK is selectable with CLKE pin polarity. See the CLKE
1. RDATA and RCLK connect the LXT384 Transceiver to a framer/mapper, while BPV acts as a
2. The receiver outputs the recovered clock at RCLK. RCLK synchronizes the data transfer into
3. RDATA does not include information about the polarity of the marks at RTIP/RRING.
4. RDATA validation relative to RCLK is selectable with CLKE pin polarity. See the CLKE pin
•
•
Low, bipolar I/O is selected.
High for more than 16 consecutive MCLK clock cycles, unipolar I/O is selected.
and negative pulses, into a sequence of logic zeroes and ones. It then outputs the resulting
information onto RNEG and RPOS.
a framer/mapper. A logic ‘1’ on:
pin description in
bipolar violation detector. The LXT384 Transceiver internally decodes HDB3/AMI.
the framer/mapper.
description in
— RNEG indicates that a negative pulse is detected on the line, and corresponds to the
— RPOS indicates that a positive pulse is detected on the line, and corresponds to the receipt
— The receiver outputs the recovered clock at RCLK. RCLK synchronizes the data transfer
receipt of a negative pulse on RRING/RTIP.
of a positive pulse on RRING/RTIP.
into the framer/mapper.
Table 11, “Clocks and Clock-Related Signals” on page
lists receive-side framer/mapper signals, which can connect to a framer/mapper
Table 11, “Clocks and Clock-Related Signals” on page
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Table 8
lists details.
37.
37.
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