DJLXT384LE Intel, DJLXT384LE Datasheet - Page 52
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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Intel
6.4
6.4.1
52
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Transmitter
The LXT384 Transceiver has eight identical transmitters.
Transmitter Clocking
The eight low-power transmitters of the LXT384 Transceiver are identical. Transmit data is
clocked serially into the device at TPOS/TNEG in bipolar mode, or at TDATA in unipolar mode.
For each channel, the transmit clock (TCLK) supplies the transmitter input synchronization.
When TNEG/UBS is connected:
The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer to the
Section 5.5, “Clocks and Clock-Related Signals” on page 37
characteristics.
•
•
High for more than 16 consecutive MCLK clock cycles, unipolar I/O and HDB3/B8ZS/AMI
encoding/decoding is used. In this case, transmit data are clocked serially into the LXT384
Transceiver at TPOS/TDATA, and the LXT384 Transceiver routes the transmit clock and data
signals to its internal encoder.
To an output that supports bipolar mode, the line does not exhibit more than 1 bit
consecutively high for any period of time and the LXT384 Transceiver automatically defaults
to bipolar operation. Transmit data are clocked serially into the LXT384 Transceiver at TPOS/
TNEG.
for MCLK and TCLK timing
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
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