DJLXT384LE Intel, DJLXT384LE Datasheet - Page 85
DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
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Document Number: 248994
Revision Number: 005
Revision Date: November 28, 2005
Table 47. AIS Status Monitor Register, AIS - 13h
Table 48. AIS Interrupt Enable Register, AISIE - 14h
Table 49. AIS Interrupt Status Register, AISIS - 15h
Bit
7:0
Bit
7:0
Bit
7:0
AISIE7:0
AISIS7:0
AIS7:0
Name
Name
Name
Alarm Indication Signal Status Monitor.
Alarm Indication Signal Interrupt Enable.
Alarm Indication Signal Interrupt Status.
• On power-up, all AIS7:0 bits are cleared to ‘0’.
• All AIS interrupts are cleared by a single read operation.
• Each time a channel receiver detects an AIS condition, its corresponding
• On power-up, all AISIE7:0 bits are cleared to ‘0’.
• When an AISIE bit is set to ‘1’, it enables an AIS interrupt for its
• On power-up, all AISIS7:0 bits are cleared to ‘0’.
• Each time there is a change in the AIS status of a receiver, its
• After the host processor reads this register, all AISIS bits clear to ‘0’.
AIS bit is set to ‘1’.
corresponding receiver.
corresponding AISIS bit is set to ‘1’.
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Description
Description
Description
R/W
R/W
R/W
R/W
R
R
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