DJLXT384LE Intel, DJLXT384LE Datasheet - Page 4
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DJLXT384LE
Manufacturer Part Number
DJLXT384LE
Description
Manufacturer
Intel
Datasheet
1.DJLXT384LE.pdf
(140 pages)
Specifications of DJLXT384LE
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Contents
7.0
8.0
9.0
10.0
11.0
4
6.6
6.7
6.8
6.9
6.10
Operating Mode Summary
7.1
7.2
7.3
7.4
7.5
Registers
8.1
8.2
8.3
JTAG Boundary Scan
9.1
9.2
9.3
9.4
Electrical Characteristics
Timing Characteristics
11.1
11.2
11.3
Jitter Attenuation ................................................................................................. 60
Loopbacks ........................................................................................................... 62
6.7.1
6.7.2
6.7.3
Transmit All Ones Operations ............................................................................. 65
6.8.1
6.8.2
6.8.3
Performance Monitoring ...................................................................................... 67
Intel
Interfacing with 5V Logic ..................................................................................... 69
Hardware Mode................................................................................................... 69
Hardware Mode Settings..................................................................................... 70
Host Processor Modes ........................................................................................ 71
7.4.1
7.4.2
Interrupt Handling................................................................................................ 74
7.5.1
7.5.2
7.5.3
Register Summary .............................................................................................. 75
Register Addresses ............................................................................................. 77
Register Descriptions .......................................................................................... 78
Overview ............................................................................................................. 86
Architecture ......................................................................................................... 86
TAP Controller..................................................................................................... 87
JTAG Register Description.................................................................................. 89
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
Intel
Host Processor Mode - Parallel Interface Timing.............................................. 109
11.2.1 Intel
11.2.2 Motorola* Processor - Parallel Interface Timing................................... 115
Host Processor Mode - Serial Interface Timing ................................................ 121
...................................................................................................................... 75
®
®
Hitless Protection Switching ...................................................................... 68
LXT384 Transceiver Timing .................................................................... 106
Analog Loopback ................................................................................... 62
Digital Loopback..................................................................................... 63
Remote Loopback .................................................................................. 64
TAOS Generation................................................................................... 65
TAOS Generation with Analog Loopback .............................................. 66
TAOS Generation with Digital Loopback................................................ 66
Host Processor Mode - Parallel Interface............................................... 71
Host Processor Mode - Serial Interface ................................................. 73
Interrupt Sources.................................................................................... 74
Interrupt Enable...................................................................................... 74
Interrupt Clear ........................................................................................ 74
Boundary Scan Register (BSR).............................................................. 89
Analog Port Scan Register (ASR) .......................................................... 94
Device Identification Register (IDR) ....................................................... 94
Bypass Register (BYR) .......................................................................... 94
Instruction Register (IR) ......................................................................... 95
®
Processor - Parallel Interface Timing ......................................... 109
............................................................................................. 86
......................................................................................... 105
...................................................................................... 96
................................................................................... 69
Revision Date: November 28, 2005
Document Number: 248994
Revision Number: 005
Datasheet