82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 76

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.18.2
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSD pin is used to input the data at the bit rate of 2.048 Mb/s. While in
the Multiplexed Mode, the data is byte interleaved from one high speed
data stream and inputs on the MTSD pin at the bit rate of 8.192 Mb/s.
transmit system interface is in Transmit Clock Slave mode, otherwise if
the device outputs clock to TSCK itself, the transmit system interface is
in Transmit Clock Master mode.
Table 43: Operating Modes Selection In E1 Transmit Path
3.18.2.1
pin and framing pulse on the TSFS pin are used to input the data on the
TSD pin. The signaling bits on the TSIG pin are per-timeslot aligned with
the data on the TSD pin.
face is clocked by the TSCK. The active edge of the TSCK used to
update the pulse on the TSFS is determined by the FE bit. The active
edge of the TSCK used to sample the data on the TSD and TSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFS is ahead.
Basic frame, CRC Multi-frame and/or Signaling Multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFS is
selected by the FSINV bit.
mit Clock Master Full E1 mode and Transmit Clock Master Fractional E1
mode.
3.18.2.1.1
Master mode, the special feature in this mode is that the TSCK is a stan-
dard 2.048 MHz clock, and the data in all 32 timeslots in a standard E1
frame are clocked in by the TSCK.
3.18.2.1.2
Master mode, the special feature in this mode is that the TSCK is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
IDT82P2281
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
TMUX
0
1
In E1 mode, the Transmit System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the TSCK is from outside, the
In the Transmit Clock Master mode, the timing signal on the TSCK
In the Transmit Clock Master mode, the data on the system inter-
In the Transmit Clock Master mode, the TSFS can indicate the
The Transmit Clock Master mode includes two sub-modes: Trans-
Besides all the common functions described in the Transmit Clock
Besides all the common functions described in the Transmit Clock
E1 MODE
TMODE
Transmit Clock Master Mode
X
0
1
Transmit Clock Master Full E1 Mode
Transmit Clock Master Fractional E1 Mode
not both 0s
G56K, GAP
00
X
X
1
Transmit Clock Master Full E1
Transmit Clock Master Fractional E1
Transmit Clock Slave
Transmit Multiplexed
Operating Mode
76
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCK, the Transmit System Interface is in Transmit Clock
Master Fractional E1 mode.
various operating modes and the pins’ direction of the transmit system
interface in different operating modes.
selecting the G56K & GAP bits in the Transmit Payload Control. The
data in the corresponding gapped duration is a don't care condition.
3.18.2.2
pin and the framing pulse on the TSFS pin to input the data on the TSD
pin are provided by the system side. The signaling bits on the TSIG pin
are per-timeslot aligned with the data on the TSD pin.
is clocked by the TSCK. The active edge of the TSCK used to sample
the pulse on the TSFS is determined by the FE bit. The active edge of
the TSCK used to sample the data on the TSD and TSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
TSFS is ahead. The speed of the TSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 Mb/s) or
double the data rate (4.096 Mb/s). If the speed of the TSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to sample the data on
the TSD and TSIG pins. The pulse on the TSFS pin is always sampled
on its first active edge.
frame, CRC Multi-frame and/or Signaling Multi-frame. The indications
are selected by the FSTYP bit. The active polarity of the TSFS is
selected by the FSINV bit. If the pulse on the TSFS pin is not an integer
multiple of 125 µ s, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is ‘1’.
3.18.2.3
transmit the data to the link. The data of the link is byte-interleaved input
In the Transmit Clock Master mode, if TSCK outputs pulses during
Table 43 summarizes how to set the transmit system interface into
The TSCK is gapped during the timeslots or the Bit 8 duration by
In the Transmit Clock Slave mode, the timing signal on the TSCK
In the Transmit Clock Slave mode, the data on the system interface
In the Transmit Clock Slave mode, the TSFS can indicate the Basic
In the Transmit Multiplexed mode, one multiplexed bus is used to
MTSCK, MTSFS, MTSD, MTSIG
Transmit Clock Slave Mode
Transmit Multiplexed Mode
TSCK, TSFS, TSD, TSIG
TSD, TSIG
Input
Transmit System Interface Pin
August 20, 2009
TSCK, TSFS
Output
X
X