NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet
NSK70721PE.C2
Specifications of NSK70721PE.C2
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NSK70721PE.C2 Summary of contents
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SK70725/SK70721 Enhanced Multi-Rate DSL Data Pump Chip Set The Enhanced Multi-Rate DSL Data Pump (EMDP variable-rate transceiver that provides symmetric full-duplex communication on one twisted wire pair using a 2B1Q line code with echo-cancellation. The EMDP operates in ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Contents 1.0 Features ......................................................................................................................... 7 2.0 Pin Assignments and Signal Descriptions 3.0 Functional Description 3.1 Component Description.......................................................................................17 3.1.1 Integrated Analog Front End ..................................................................17 3.1.2 Enhanced MDSL Digital Signal Processor .............................................18 3.1.3 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figures 1 SK70725/SK70721 Block Diagram ....................................................................... 7 2 Package Markings................................................................................................. 8 3 IAFE Pin Locations................................................................................................ 9 4 EDSP Pin Assignments....................................................................................... 11 5 EDSP/IAFE Interface – Relative Timing.............................................................. 21 6 MDSL System ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Tables 1 IAFE Pin Assignments/Signal Descriptions........................................................... 9 2 EDSP Pin Assignments/Signal Descriptions .......................................................11 3 2B1Q Pulse Coding Rule ....................................................................................18 4 EDSP/IAFE Serial Control Port Word Bit Definitions...........................................20 5 EMDP Data Mode ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Revision History Revision Date 6 Description Datasheet ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 1.0 Features • Fully integrated, 2-chip transceiver. Compliant with the following standards: — ITU G.991.1 — ANSI Committee T1E1.4-TR28 (T1E1.4/96-006) — ETSI ETR-152 • Integrated line drivers, filters and hybrid circuits ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 2. Package Markings LOT # FPO # Package Topside Markings Marking Part # Unique identifier for this product family. Identifies the particular silicon “stepping” — refer to the specification update ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 2.0 Pin Assignments and Signal Descriptions The IAFE is packaged pin PLCC. signal descriptions for each pin, except pins 18 and 19, which are not connected. The EDSP ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 1. IAFE Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 13 RTIP 14 RRING 16 BTIP MDSL I/F 17 BRING 21 TTIP 22 TRING 7 XO PLL ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 4. EDSP Pin Assignments * RFP RDATA ADDR3(ACTVNG) * RDATA_ST TDATA * TFP MSTR_CK SLAVE_CK MODE_S1 MASTER * BIT_CLK NOTES: 1. Pin Functions in Hardware Control mode are shown in ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 2. EDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 16 MASTER Mode Select 15 MODE_S1 29 MODE_S2 31 MODE_S3 Status 30 ACTIVE Indication 14 SLAVE_CLK Clock and Control 13 ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 2. EDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 7 UNUSED 8 RDATA 10 UNUSED Data I/F (Transparent 11 TDATA Modes) 12 QUAT_CLK 17 BIT_CLK 7 RQUAT_CLK 8 RDATA ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 2. EDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 4 QUIET Hardware 5 ACTREQ Interface Signal Description (Hardware 6 LOOPID Control Mode only) 9 ACTVNG 1. This input is ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 2. EDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 32 TMR_EXP 33 HWSEL1 34 HWSEL2 35 HWSEL3 36 LOS 37 DEACTVTD Hardware 38 ILMT Interface Signal Description (Hardware Control ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 2. EDSP Pin Assignments/Signal Descriptions (Continued) Group Pin # Symbol 4 ADDR0 5 ADDR1 6 ADDR2 9 ADDR3 32 INT 33 CHIPSEL Processor Interface 34 WRITE 35 READ (Processor 36 ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 3.0 Functional Description The Enhanced MDSL Data Pump (EMDP) chip set provides synchronous, full duplex data transport on a single twisted wire pair using 2B1Q line coding and echo cancellation. The ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set the line code its name (1Q). pulse amplitudes to bit pairs. Note that one bit of the pair is used to set the sign (the sign bit), while the second bit ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 2 lists the EDSP pin descriptions. Refer to Test Specifications for EDSP electrical and timing specifications. 3.1.2.1 Scrambling The transmitted 2B1Q symbol must change value frequently to maintain appropriate power ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 3.1.3.1 Serial Control Port The EDSP continually writes to the serial control port via SER_CTL signal stream. This serial control stream consists of two 16-bit words as shown in the IAFE ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 5. EDSP/IAFE Interface – Relative Timing A) EDSP/IAFE Interface - Transmit Timing 1 2 TX_CLK TSGN TMAG IAFE Sampling Edge B) EDSP/IAFE Interface - Receive Timing VCO_CLK VCO_CLK/2 AD0 AD1 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 3.1.4 Line Interface The Data Pump line interface consists of three differential pairs. The transmit outputs TTIP and TRING, receive inputs RTIP and RRING, and the balance inputs BTIP and BRING, ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 6. MDSL System Data Transport (Framed Mode Shown) BIT_CK b4701 b4702 XXX TDATA TFP TDATA TFP BIT_CK RFP RDATA RDATA_ST Master Data Pump 3.1.5.1 Transparent Mode Transparent operating modes are ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set • Provides an MDSL frame position indicator that may be used in time-division-multiplexed systems to relate time slots in the MDSL frame to those in an application frame (See Note above). ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 8. Framing with and without stuff bits(4,702 bits per frame example) Short Frame Frame Sync Word Long ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 7. Register Summary ADDR Write Registers A3-A0 WR# Name 0000 WR0 Main Control 0001 reserved Interrupt Mask and Line 0010 WR2 Reversal Coefficient Select and 0011 WR3 Activation Timer 0100 ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 8. Main Control Register (WR0) Bit Transmit Test Pulse Enable (TXTST). Set TXTST transmit isolated pulses. TDATA controls the sign and TFP controls the magnitude of the ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 9. Interrupt Mask and Line Reversal Control Register (WR2) Bit TRREV. TIP/RING reversal control. Set invert B7 the polarity of the received signal. B6 Reserved. Must be ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 11. Coefficient Select Functions of Register (WR3) (Continued) B4:B0 in Register hex Selected 16-19 reserved 1A AGC Tap 1B:1F reserved 3.1.6.4 WR9—Gain Control Register Address: A<3:0> = 1001 Default: 00h ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 13. Micro-interruption Timer Register (MITR) Bit Eight Most Significant Bits (MSB) of the Micro- B7:B0 interruption timer. Table 14. Activation Sub-State Timer Registers Register Address Timer Name A3-A0 1010 SMT1 ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 15. Main Status Register (RD0) (Continued) Bit Deactivation Indicator (DEACTVTD). Set EDSP to indicate expiration of the Deactivation timer and the transition from the Pending Deactivation state ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 16. AGC Tap Value Register (RD1) Bit FFE AGC Tap Value (eight most significant bits AGC Tap Sign bit - always = AGC Tap MSB, ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 17. Noise Margin Register (RD2) (Continued) MSB LSB Coded Noise Margin ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 19. Activating Status Register (RD5) (Continued) Bit 0010 0011 0100 0101 0110 0111 1000 0000 1. Available only in operating mode 6 and 7. In other operating modes this state ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 . Table 21. Data Pump Activation State ST2 ST1 During Active State, received data is available ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set • The internal scrambler disabled, magnitude bit transmitted first (mode #1). • The internal scrambler enabled, sign bit transmitted first (mode #2). When the internal scrambler is disabled, the incoming data ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Independent mode has another option, to enable or disable the internal scrambler. If the scrambler is bypassed, the user must assure that the 2B1Q pulses are properly scrambled to meet the ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set structure for three pair HDSL systems. Both framing modes provide bit stuffing capability so that pleisiochronous data streams may be transported without error and with acceptable jitter and wander. The scrambler ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 14. Clock/Data Relationships: Framed Mode (#6), Scrambled (7006/7010 bits per frame) A) Transmit Timing–Without Stuff Bits BIT_CK TFP b7003 b7005 TDATA b7004 b7006 b1-b14 are the frame sync word generated ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 15. Clock/Data Relationships: Framed Mode (#7), Scrambled (4702/4706 bits per frame) A) Transmit Timing–Without Stuff Bits BIT_CK TFP b4699 b4701 TDATA b4700 b4702 b1-b14 are the frame sync word generated ...
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... Control Modes The EMDP includes an integrated, hardware controlled state machine unique to Intel DSL Data Pumps. The hardware control mode allows the design of low cost, low power MDSL systems which do not require the support of a microprocessor. Thus, in the hardware control mode no programming is required ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 3.2.3.1 Hardware (Stand-alone) Control In hardware control mode the EMDP utilizes I/O pins to provide simple activation control and status indication. These I/O pins are multiplexed with the pins used for ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 BELB Setting BELB pin high enables Data Pump to configure in back end loop back. The Data Pump must be in active state. RDATA and RFP outputs are used in place ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Read: Data is placed on the data bus when the Data Read pin (READ) goes low. When READ is asserted, the EDSP data bus lines go from tristate to active and ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 3. Pull READ low. 4. After observing minimum pulse width make READ high to complete the read cycle. 35). Registers RD3 and RD4 hold the coefficient values from the DFE, EC, ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 18. Activation State Machine for Modes 0,1,2,4 & 5 LOS timer expires in Master Mode. LOS: 0 1in Slave Mode. Deactivated State (1,0,1) TX:off RX:on MIT Expires Time-out State (1,1,1) ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 19. Activation State Machine for Modes 6 & 7 LOS timer expires in Master Mode. LOS Slave Mode. Deactivated (1,0,1) TX:off RX:off MIT Expires Deactivation timer expires ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Starting from the Inactive state, the device normally progresses through the Activating, Active1, and Active2 states. In software mode, the STn bits in register RD6 shows the current status of the ...
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... Since low error rates cannot be achieved until training is completed, data output is suppressed until the Active1 state is entered in accordance with industry standards. The EMDP, like all Intel DSL Data Pumps, continuously adapts all receiver elements except the AGC in the Active states. This allows the EMDP to perform well in the presence of significant changes in line conditions ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 23. Details of Activating State (Continued) EMDP Master States ACT Bits RD5 Receiver [3:0] State Description State Waits for receipt of 0011 SIGDET signal from Slave 0100 AAGC Trains analog ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 transmit S0 just as the Master gets to the SIGDET state and the change in the Master MAT will be minimal. If the Slave is reset or connected to the line ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 21. MDSL Activating State Detail - Framed Modes 6 and 7 Master LOS=1 Inactive (0000) Activating ACTREQ 0 1 SMT1 Pre-AGC(0001) SMT2 Pre-EC (0010) LOS=0 1 TDELTA SIGDET (0011) Data ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 from the Master. On receipt of this signal the Slave completes training of the DFE and 4 level slicer then begins to transmit an S1 signal. The Master detects the S1 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Framed Signal (Modes 6,7) Both Master and Slave move directly to the FRAMEDET sub-state on completion of the 4LVLDET training functions. The devices begin executing their internal algorithm to search for ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 26. State Machine Default Timer Durations (Figure 18 and Figure 19) 1 Default Timer Duration (seconds) Timer 272 400 528 kbps kbps kbps 2 MAT 86.5 59.0 44.5 Deactivation 6.0 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set the EMDP goes directly back to State 0. An Out-of-Sync condition is declared in State 6, which is reached when no FSW is detected for six consecutive frames. As soon as ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 3.2.7 Deactivation The EDSP may be deactivated by using control signals to stop transmission on the loop or by the expiration of MAT. This section describes method of deactivation. “Normal” Deactivation ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set System manufacturers should determine the value for MIT which provides good recovery performance in the test circumstances of interest. Larger values of MIT may be effective in some circumstances, but not ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 28. MIT Register Setting Example Baud Line Rate Increment value Period (kbps) (msec) ( sec) Desired MIT (msec): 272 7.35 15 400 5.00 10 528 3.78 8 784 2.55 5 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 3.3.4 Loop Loss and SNR In software control mode, EMDP provides information to compute approximate loop loss and SNR. The approximate loop loss (LL) can be calculated as follows ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 24. Loopbacks A) Front end loopback (FELB) EDSP TDATA, TFP RDATA, RFP B) Back-end loopback (BELB) EDSP TDATA, TFP BELB RDATA, RFP Note: FELB is also known as local loopback ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 4.0 Application Information 4.1 PCB Layout The following are general considerations for PCB layout using the EMDP chip set: • Refer to Figure 25 • Use a four-layer or more PCB ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 — TTIP/TRING — BTIP/BRING — RTIP/RRING • Do not run the analog ground plane under the transformer line side to maximize high voltage isolation. • The IAFE should be placed such ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 25. PCB Layout Guidelines (Figure 26 for schematic) VCC GND D2 C11 R13 D1 C10 R11 NOTE: The VCC and GND planes for Digital and Analog sides should be connected ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 26. Typical Application (Software Mode) + MDSL DATA I/F 7 RFP 10 TSGN RDATA_ST 8 TMAG RDATA 17 TX_CLK BIT_CLK 12 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 29. Components for Typical Application (Figure 26) (Continued) Ref Description 470 pF, COG or mica, C7, 8 10% C4-6, 9 0.1 F, ceramic, 10% C1 100 F, electrolytic, 20% Figure ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 30. Components for Typical Application (Figure 27) Ref Description C2 0.01 F, ceramic, 10% 100 F, electrolytic, 20% C13 low leakage A @ 25° C C14, 15 1000 ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 4.2.2 Crystal Specifications Typical Crystal Specifications Table 32. Parameter Frequency @ Fundamental, Parallel Mode Pullability Õ pF) L Operating Temperature Temperature Drift ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 5.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the EMDP and are guaranteed by test, except where noted by design. Table 34. IAFE Absolute ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 37. IAFE Transmitter Electrical Parameters (Over Recommended Range) Parameter Sym – – Isolated pulse height at TTIP, TRING – – Setup time (TSGN, TMAG) t TSMSU Hold time (TSGN, TMAG) ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 29. Transmit Power Spectral Density—Upper Bound -20 - dBm/ kHz - dBm/Hz @ 100 kHz - 35 dBm/Hz -80 @ 132 kHz -37 dBm/Hz ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 30. Typical Performance vs. Line Rate and Cable Gauge (Metric) 8,000 7,500 7,000 6,500 6,000 5,500 5,000 4,500 4,000 3,500 3,000 2,500 2,000 NOTES: 1. Noise-free range is specified with ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 31. Typical Performance vs. Line Rate and Cable Gauge (English) 30,000 25,000 20,000 15,000 10,000 5,000 NOTE: 1. Noise-free range is specified with a BER less than or equal to ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 40. EDSP Recommended Operating Conditions Parameter 1 DC supply Ambient operating temperature Table 41. EDSP DC Electrical Characteristics (Over Recommended Range) Parameter 272 kbps 400 kbps Supply current 528 kbps ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Table 42. EMDP Data Interface Timing Specifications (Continued) Parameter BIT_CLK, TBIT_CLK, and RBIT_CLK pulse 3 width (high) 272 kbps 400 kbps 528 kbps 784 kbps 1168 kbps BIT_CLK and TBIT_CLK delay ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Figure 32. EDSP Clock and Data Interface Timing A) Clock Timings MASTER_CLK T MBDLY BIT_CLK, TBIT_CLK T BQDLY QUAT_CLK, TQUAT_CLK B) Timings in Framed Modes 6 and ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 33. EDSP Data Interface Timing A) Timings in Transparent Mode 0, 1 and 2 BITCLK (output) TDATA (input) RDATA (output) B) Timings in Independent Modes 4 and 5 TBIT_CLK (output) ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 43. EDSP/Microprocessor Interface Timing Specifications (Continued) Parameter CHIPSEL setup to READ falling edge. CHIPSEL hold from READ rising edge. CHIPSEL setup to WRITE rising edge. CHIPSEL hold from WRITE rising ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 35. EDSP Read and Write Timing (Processor Control Mode A) Data Read Timing T CHIPSEL READ T ADSUR ADDR <0:3> D <0:7> Output INT B) Data Write Timing CHIPSEL WRITE ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set Table 44. General System and Hardware Mode Timing Parameter 272 kbps Throughput delay from 400 kbps TFP of Master to RFP of 528 kbps Slave in framed modes 6 784 kbps ...
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Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721 Figure 37. Data Pump Package Specifications Integrated Analog Front End (IAFE) • 28 pin PLCC • P/N SK70721PE (-40° to ...
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SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set 6.0 Acronyms Table 45. Acronyms Acronym ACTREQ BELB BER COFA DFE EC EDSP EMDP FFE FSW FELB ILMT IAFE LL LOOPID LOS MAT MATC MIT MITR MSB PLL RFP RPTR SNR ...