NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 45

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.2.5
3.2.5.1
Datasheet
Registers RD3 and RD4 hold the coefficient values from the DFE, EC, FFE and AGC as shown in
Table
reconstruct the complete 16-bit word, concatenate the least significant and most significant bytes.
To read registers RD3 and RD4:
Activation
The EMDP integrates all logic required to manage DSL line activation, operation, and
deactivation.
5).
major states shown in
Deactivation) have significant sub-states which can be managed for optimum performance. The
Activating Substates are described in the following:
21.
Activation can be initiated only at the Master Data Pump.
Earlier MDSL Data Pumps operated only in Framed mode. These Data Pumps used FSW, for
activation state timing. These Data Pumps also relied on detection of the FSW for changes from
one state to another. The EMDP uses the FSW in the activation sequence only in framed modes 6
and 7.
Activation Sequence
When the Master Data Pump is reset, the EMDP goes to the Inactive state. The EMDP remains in
the Inactive state until the ACTREQ command is asserted. In the hardware mode when the Master
Data Pump is in the Inactive state and the QUIET pin is low, a low-to-high transition on the
ACTREQ pin initiates activation of the link. In the software mode when the Data Pump is in the
Inactive state and the QUIET bit is set to 0, setting the ACTREQ bit to 1 initiates activation of the
link. Because the ACTREQ control bit is level sensing, to generate a single request, ACTREQ
should be set to 1 and then reset to 0 before the MAT expires.
The activation state machines for Slave and Master EMDP are similar. The primary difference is
that the Master activates from and external activation command (ACTREQ) while the Slave device
begins activation when signal energy is detected on the loop. Thus, only the Master device can
bring up the link. Once the Master begins transmitting, the Slave device will automatically activate
and attempt synchronization.
3. Pull READ low.
4. After observing minimum pulse width make READ high to complete the read cycle.
1. Select the desired coefficient by writing the appropriate code from
2. Enable the Coefficient Read Register by writing a 1 to bit b0 (CRD1) in register WR2.
3. Perform standard register read procedure listed in steps 1 through 6 above to read the lower
4. Concatenate the contents of RD3 and RD4 to obtain the complete 16-bit word.
Figure 19
35).
byte from RD3 and the upper byte from RD4.
11. Register RD3 holds the lower byte value and register RD4 holds the upper byte value. To
illustrates the Activation State Machine for framed modes (6 and 7). In addition to the
Figure 18
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
Figure 18
illustrates the Activation State Machine for unframed modes (0,1,2,4, and
and
Figure
19, two of the EDSP states (Activating and Pending
Table 23
and
Table
Table 11
24,
Figure 20
to register WR3.
and
(Figure
Figure
45