NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 23

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.1.5.1
3.1.5.2
3.1.5.3
Datasheet
Figure 6. MDSL System Data Transport (Framed Mode Shown)
BIT_CK
TDATA
TFP
Transparent Mode
Transparent operating modes are used for the transport of asynchronous data or fully synchronous
data (which may have been framed by an external device). All Transparent modes have common
transmit and receive clocks and provide an optional internal scrambler/descrambler. If the
scrambler is bypassed, the application must align the data appropriately to ensure that the correct
2B1Q symbol is transmitted. Data may be input with either the sign or magnitude bit first.
The appropriate selection of mode enables operation compatible with other vendor’s framers. In
this mode the use of a single clock for transmit and receive data results in small, but uncontrolled,
data delays.
Independent Mode
In Independent timing mode the EMDP provides separate transmit and receive clocks at the data
interface. Both clocks are at the same rate, but the clock phases are independent. In this mode,
minimum delay of the data is assured. In addition, delay is constant for subsequent activations on
the same loop. Constant delay is necessary for applications such as alignment of transmitted signals
from radio base stations where data delay must be precisely measured and controlled. An optional
internal scrambler is available in Independent mode.
Framed Mode
Framed mode is provided for compatibility with previous MDSPs and HDXs - SK70720,
SK70706, SK70707, and SK70708. Framed mode is useful for applications in which
pleisiochronous data must be transmitted while maintaining accurate timing information.
The EMDP can embed a 14-bit Frame Synchronization Word (FSW) and optional stuffing bits in
the data stream that divides the data into MDSL frames with average length of 4704 or 7008 bits as
shown in
•
Transports plesiochronous data, where data rate is not precisely related to the line rate and the
data rate in each direction of transmission is different while retaining frame alignment.
b4701
Figure
b4702
Master Data Pump
XXX
TDATA
TFP
BIT_CK
RFP
RDATA
RDATA_ST
7. The Framed mode, with associated stuffing, provides two primary functions:
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
X
XXXXX
b15
b16
Scrambled 2B1Q
Signal
RDATA_ST
BIT_CK
RDATA
RFP
Slave Data Pump
RDATA_ST
BIT_CK
RDATA
TDATA
b4701
RFP
TFP
b4702
b15
b16
23